Abstract: In order to measure the in-plane thermal conductivity of a sample plate, the plate is placed in a prefabricated device containing (1) a pair of thermocouples, (2) a source of heat flow into the plate, (3) a heat sink of the heat flow having an open cavity, (4) a taut membrane, on which the source of heat flow and the thermocouples are bonded, located on the resilient filling, (5) a resilient filling of thermally insulating material located underneath the membrane, in the cavity of the heat sink, and (6) a thermally insulating medium covering the plate and exerting a compressive force on it.

Abstract: A direct-writing electron beam is used for defining features in a resist layer and hence ultimately in an underlying workpiece, such as in a phase-shifting mask substrate or a semiconductor integrated circuit wafer. The resist layer is located on a top major surface of the workpiece.In a specific embodiment, the resist layer is located underneath a protective layer of polyvinyl alcohol ("PVA"); and a grounded conductive layer, such as a conductive organic layer, is located on the protective layer. After exposing the top major surface of the resulting structure to the direct-writing electron beam, the following steps are performed:(1) a plasma etching completely removes the entire thickness of the conductive layer as well as a small fraction of the thickness of the PVA layer;(2) the PVA layer is then completely removed by dissolving it in water;(3) another plasma etching removes a small fraction of the thickness of the resist layer, including any unwanted residues; and(4) the resist layer is developed.

Abstract: A phase-shifting lithographic mask is made by a procedure involving only a single patterned electron, ion, or photon beam bombardment of a resist layer. The bombardment is arranged to produce three kinds of regions in the resist: no dosage, low dosage, and high dosage. These three regions in the resist are then utilized--in conjunction with an ordinary wet development step followed by either a silylation or an optical flooding technique, and thereafter by another ordinary wet development step--to pattern the resist layer and thereby to enable forming, by dry or wet etching, an underlying double layer consisting of a patterned opaque layer and a patterned transparent phase-shifting layer, the phase-shifting layer being located on, or being part of, a transparent substrate.

Abstract: A nickel plug (31) filling an aperture in an insulating layer (30), such as polyimide, separating two metallization levels of copper wires (28, 25) is formed by an electroless process in a plating bath (solution) containing ions of hypophosphite and of nickel. In preparation for this electroless process, the copper wires (28, 25) are first plated with a nickel layer (29) by a pseudo-electroless process-that is, a process in which the copper wires (28, 25) are located in contact with an underlying extended chromium layer (14) that is placed in electrical contact (including intimate physical contact) with an auxiliary metallic member (41) that contains nickel, while both the copper wires (28, 25), the chromium layer (14), and at least a portion of the external metallic layer (41) are immersed in a plating solution likewise containing ions of hypophosphite and of nickel.

Abstract: A defect in the form of excess material, located in a trench region at a major surface of a phase-shifting mask, is removed by spinning on the major surface a planarization layer for which dry-etching conditions exist at which it anisotropically etches at the same rate as that of the excess material. Then the planarization layer is dry-etched under those conditions, using a patterned protective masking layer, such as chrome, having an aperture overlying the defect in the trench. This aperture need not be precisely laterally aligned with the defect (unless the defect extends to an edge of the trench). A plurality of such defects can be simultaneously removed. Likewise, defects located on plateau regions of the mask can be repaired.

Abstract: A phase-shifting mask, having plateau and trench surfaces located on a major surface of the mask, has a defect in the form of an indentation region located on a plateau (or trench) surface. The mask is repaired with respect to the defect by spinning on the major surface of the mask a planarization layer for which dry-etching conditions exist at which this planarization layer anisotropically etches at the same rate as that of the mask substrate material--e.g., quartz. Then the portion of the planarization layer overlying the defect is dry-etched under those conditions, using in one embodiment a patterned protective masking layer, such as chrome, having an aperture overlying the defect. This aperture need not be precisely laterally aligned with the defect (unless the defect extends to an edge of the plateau surface). The etching is continued until it reaches a depth H beneath the level of the plateau (or trench) surface that is equivalent to a phase shift of 2n .pi.

Abstract: A phase-shifting lithographic mask is made by a procedure involving only a single patterned electron, ion, or photon bombardment of a resist layer. The bombardment is arranged to produce three regions in the resist containing mutually different bombardment doses per unit area, one of which is typically zero. These three regions are then used--in conjunction with separate wet development steps with two developers of different concentrations--in order to pattern the resist layer and to from an underlying double layer consisting of a patterned opaque layer located on a differently patterned transparent phase-shifting layer, the transparent phase-shifting layer being located on, or being part of, a transparent substrate.

Abstract: The remaining capacity of a storage cell, particularly a valve regulated lead-acid cell, is determined by measuring its impedance at typically two or three relatively low frequencies f, e.g., frequencies in the approximate range of 0.001 to 1.0 Hz. In one application, the imaginary part Z" of the complex impedance Z(=Z'+jZ") is plotted vs. f.sup.-1/2, whereby the intercept Z".sub.o (at f.sup.-1/2 =0) of the bestfitting straight line of the plot is a measure of the cell's remaining capacity. In another application, the slope (dZ"/dZ') of a plot of the imaginary part Z" vs. real part Z' of the complex impedance Z, again as measured at relatively low frequencies f, is a measure of the cell's remaining capacity.

Abstract: A field programmable array of application circuitry (C1, C2, . . .) is programmed (or reprogrammed) by first applying application circuitry power supply (AV.sub.dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is typically one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The source-drain path of each pass transistor is connected between a separate pair of application circuitry interconnection points (A1, A2), whereby the on/off condition of this pass transistor determines whether or not these two points are going to be connected after the programming (or reprogramming) is terminated.

Abstract: A laser device is bonded to a diamond submount by means of a procedure including (1) codepositing an auxiliary layer, on a layer of barrier metal that has been deposited overlying the submount, followed by (2) depositing a wetting layer on the auxiliary layer, and (3) by depositing a solder layer comprising alternating metallic layers, preferably of gold and tin sufficient to form an overall tin-rich gold-tin eutectic composition. The barrier metal is typically W, Mo, Cr, or Ru. Prior to bonding, a conventional metallization such as Ti-Pt-Au (three layers) is deposited on the laser device's bottom ohmic contact, typically comprising Ge. Then, during bonding, the solder layer is brought into physical contact with the laser device's metallization under enough heat and pressure, followed by cooling, to form a permanent joint between them. The thickness of the solder layer is advantageously less than approximately 5 .mu.m. The wetting layer is preferably the intermetallic compound Ni.sub.3 Sn.sub.

Abstract: One or more metallized chip terminals of an electronic device, such as an integrated circuit chip or a laser chip, in one embodiment are temporarily bonded to one or more metallized substrate pads of a wiring substrate, as for the purpose of electrically testing the electronic device. The composition of the metallized chip terminals is suitably different from that of the metallized substrate pads. The pads and terminals are aligned and electrically connected together with a solder located between them under pressure and a temperature above the melting point of the solder. The solder is cooled, and electrical tests of the electronic device are performed by means of electrical access from testing circuitry to the chip terminals through the substrate pads.

Abstract: A laser assembly including a diamond film submount is formed by anisotropically etching a localized indentation (recess) region in an originally completely planar face of the film. The region has one or pair of intersecting sidewalls preferably making the same angle between them as an angle made between a pair of sides of a laser device. After metallizing the remaining top face of the film, the bottom of the indentation region, and one or both of the sidewalls of the indentation region, the laser device is pushed into position in the recess with its above-mentioned pair of sides lying against one of the sidewalls and the metallization of the other sidewall, or lying against the metallization of both sidewalls; and the bottom of the laser device is quickly bonded by means of solder to the metallization on the bottom of the recess.

Abstract: A choke-coil fixture for miniature motors of a type having choke coils housed in recesses formed in an end bell closing an end of a motor housing, characterized in that choke-coil housing recesses are formed in such a manner as to lock ends of the choke coils when the choke coils are inserted into the recesses in the longitudinal direction, terminals having flat portions for pushing the other ends of the choke coils at portions electrically connecting the lead ends of the choke coils, and engaging portions for locking to the end bell is disclosed. The terminals for miniature motors can have positioning portions for positioning the terminals with respect to the lead ends of the choke coils, and cylindrical portions for engaging with the connecting power-feeding connecting pins; the cylindrical portion adapted to be flexible in size by being plastically deformed.

Abstract: In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.

Abstract: A clamped linear transconductance amplifier path, consisting essentially of a current clamp merged in a linear transconductance amplifier path, is used in a triple-input, triple-output transconductor (200). In a balanced transconductor in CMOS technology, this clamped linear transconductance amplifier path is formed by a p-channel MOS transistor (M23) separately connected in series with each of a matched pair of p-channel MOS transistors (M21,M22). The clamped linear transconductance amplifier path, together with two other transconductance paths (M15-M20; M9-M14), can be interconnected to form the input side of the triple-input, triple-output transconductor (200). By summing and integrating the outputs of the input side of the triple-input transconductor (200), the output (V.sub.OUT,P and V.sub.OUT,N) of the output side of the transconductor can be formed. By feeding back this output to the input side of the transconductor (200), an oscillator can be obtained.

Abstract: Partially recessed microlenses (31, 32; FIG. 3) are made in a substrate (10) by a technique including the steps of forming a hard-baked patterned layer (21, 22, 64, FIG. 2) on a surface of the substrate, this patterned layer having at least one island portion (21, 22) surrounded by an auxiliary portion (64), and simultaneously etching this hard-baked patterned layer and the substrate to remove at least a portion of the thickness of the hard-baked layer. The island portions are located at areas overlying where microlenses are desired. The volume of the auxiliary portions of the hard-baked patterned layer is advantageously significantly greater than that of the island portions.Full recessed microlenses (31, 32; FIG. 6) are made by adding a step in the above technique, namely, the step of forming another hard-baked patterned layer (94) covering only the auxiliary portions of the above-mentioned patterned layer prior to the etching.

Abstract: Substrate-supported optical device structures such as, e.g., quantum-well infrared detectors/detector arrays are provided with a grating for optical coupling. Preferred gratings are formed in a nonepitaxial layer which, preferably, consists of a material which is different from underlying semiconductor material. Conveniently, a grating pattern is formed by etching, with the underlying material serving as an etch stop. For example, on a GaAs--AlGaAs device, polycrystalline silicon can be deposited and etched in this fashion.

Abstract: In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.

Abstract: A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12, 13 in A1, A2, A3, . . . and B1, B2, B3, . . . ). Further, the n'th one of set of clocked latches (14, 15, 16 in A2, A4, A6, . . . ) derives its input from the 2n'th one of the delay elements in the first chain, where n is a running integer index (n=1,2,3, . . . ). The circuit (100) also includes a set of two-input logic gates (11), one of whose inputs (IN) is the output (OU) of a separate one of the logic elements (12, 13) in the second chain and the other of whose inputs is an output (MO) of a separate one of the latches (14, 15, 16). Each of the outputs of these logic gates (11) is fed to a multiple input output logic gate (25) whose output has a desired double-frequency feature (edges at T/4) relative to the frequency of the clocked pulse sequence (CLK).

Abstract: A vertical-cavity surface-emitting semiconductive laser has non-epitaxial multilayered dielectric reflectors located on both its top and its bottom surfaces, in order to facilitate fabrication of the reflectors and achieve high optical cavity gain and low electrical power dissipation.