Abstract: A solid-state relay is combined with a control circuit to form a switch which is bilateral and linear through the origin, can withstand large current or voltage surges, and can be toggled either electrically or optically. The relay portion comprises either a pair of or two subsets of DMOS transistors, and the pair of transistors or selected ones of each subset cooperate to form a pair of oppositely poled thyristors. The control circuit provides well regulated turn-on and turn-off of the relay and provides good immunity against high voltage transients on the switch's main terminals. The control circuit also serves to limit the maximum voltage that is applied to the gate oxides of the transistors.

Abstract: At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaranteed to be low at the end of the precharging phase as is desired for inputs to all domino logic.

Abstract: In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as interconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventional load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. In accordance with a feature of the invention, the structural parameters of each line are selected to meet specified design criteria that ensure optimal high-frequency performance of the line.

Abstract: A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.

Abstract: An improved radial type high voltage solid-state switch is essentially a gated diode switch (GDS) having two anode regions, two gate regions, a common cathode region, and a common shield region. The anodes, gates, cathode, and shield all have sides which are portions of concentric circles. The arc lengths and radii of the anode regions are less than the corresponding arc sides of the shield and cathode. This structure, which is a dual radial gated diode swtich (DRGDS), has lower on resistance than a conventional radial gated diode switch which has the same operating voltage range.

Abstract: A transistor structure has a semiconductive base layer located between an emitter and a collector, the base layer during operation having an inversion layer therein which spreads out in directions transverse to the emitter-collector current path.

Abstract: A microprocessor with a macro-rom exhibits reduced latency time and greater flexibility by including both a macro-rom queue and a main program queue. The arrangement eliminates the undesirable latency associated with fetching program as part of a return sequence from a macro-rom instruction. Also, the arrangement allows parameters to be extracted from the main program queue as the macrosequence is executing from the macro-roms program queue.

Abstract: A resistive load element comprises a Schottky barrier metal layer formed on the top surface of a doped p-type polycrystalline silicon (polysilicon) plug contacting a surface n.sup.+ zone located in a semiconductor body at a major horizontal surface thereof. The Schottky barrier metal layer is advantageously essentially a metal compound, such as titanium nitride, which does not react with the polysilicon and which forms a Schottky barrier contact with the polysilicon top surface of the plug. The polysilicon plug extends vertically down to the n.sup.+ zone through an aperture in an insulating layer that coats the major surface of the semiconductor body. The top surface of the Schottky barrier layer is coated with another metal layer, such as aluminum, for interconnection purposes. A pair of such elements can be integrated as loads, for example, in a static random access memory ("flip-flop") cell.

Abstract: The threshold voltage of a CMOS circuit is stabilized by a feedback loop which responds to variations in threshold voltage of a reference FET to provide a backbias voltage to readjust the threshold voltage of a second FET. The circuit is particularly useful to overcome threshold variations due to .gamma.-radiation.

Abstract: Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multistage network. Without prolonging the individual phase durations or adding any registers, the added domino logic network can have a propagation delay time corresponding to more than one phase of the PLA, and hence the network can have correspondingly more stages and more added data processing capability.

Abstract: A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W.sub.1, W.sub.2 . . . W.sub.n) between AND and OR planes of the PLA and a second master-slave shift register on the output lines emanating from the OR plane. In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.

Abstract: To switch a first gated diode switch (GDSL1) to the "OFF" state requires a voltage applied to the gate which is more positive than that of the anode or cathode and a sourcing of current into the gate of substantially the same order of magnitude as flows between the anode and cathode of the first switch. Control circuitry, which uses a second gated diode switch (GDSC) coupled by the cathode to the gate of the first switch (GDSL1), is used to control the state of the first switch (GDSL1). The control circuitry also comprises a first branch circuit coupled to the anode of the GDSC and to a first potential source V1 and a second branch circuit coupled to the anode of GDSC and to a second potential source V2 which is of a lower potential than V1. The second branch circuit has a high voltage and high current capability switch in series between V2 and the anode of GDSC. The first branch circuit has a high voltage but modest current handling switch in series between V1 and the anode of GDSC.

Abstract: In order to suppress electrostatic charge buildup at a workplace, a wire having needle(s) connected thereto and extending vertically downward therefrom is suspended horizontally over the workplace, and a sequence of electrical pulses of alternating polarity is applied to the wire, each of the pulses having a pulse-width of the order of 1 second and a pulse-height of approximately 15 kilovolts.

Abstract: A random number generator (RNG) uses an edge-triggered D-type flip-flop with a high frequency square wave having an approximately 50 percent duty cycle connected to a data input terminal and a low frequency square wave connected to a clock input terminal, a five-state counter, five two-input AND gates, five exclusive-OR gates, and five shift registers. An essentially truly random number is generated at the RNG output terminals. Probability biases due to both variations in the 50 percent duty cycle of the data waveform and small amounts of cycle-to-cycle jitter of the clock waveform are effectively removed.

Abstract: An automatic gain control (AGC) amplifier circuit uses a control loop comprising a digital counter (70) which controls a multiplying digital-to-analog converter (10) arranged as an attenuator of the input v to the AGC. The counter (70) is arranged to count up or down depending upon the output signal of the AGC circuit. In addition, a latency can be introduced into the control loop so that in case of most signal envelope variations, the counter is frozen to prevent output fluctuations.

Abstract: The position (XY coordinate) of a pointed stylus on a conductive sheet is determined by injecting current from the stylus into the sheet and measuring the current responses at three or more spaced apart electrodes connected to the sheet.

Abstract: A semiconductor integrated circuit includes a nitrided silicon dioxide layer typically 50 to 400 Angstroms thick located on a semiconductor medium. The nitrided layer is an original silicon dioxide layer that has been nitrided at its top surface, as by rapid (flash) heating in ammonia to about 1250 degrees C., in such a way that the resulting nitrided silicon dioxide layer is essentially a compound layer of silicon nitroxide on silicon dioxide in which the atomic concentration fraction of nitrogen falls from a value greater than 0.13 at the top surface of the compound layer to a value of about 0.13 within 30 Angstroms or less beneath the top surface, and advantageously to values of less than about 0.05 everywhere at distances greater than about 60 Angstroms or less beneath the top surface, except that the nitrogen fraction can rise to as much as about 0.10 in the layer at distances within about 20 Angstroms from the interface of the nitrided layer and the underlying semiconductor medium.

Abstract: Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.

Abstract: In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the transistors in the string, the switching-delay is not significantly reduced by uniformly increasing the conduction channel widths of the transistors in the string. However, according to the present invention, a substantial reduction in the switching delay of such a circuit may be obtained by scaling the conduction channel widths of the transistors in the string so as to provide a positive gradient in conduction channel widths along the string in the direction from the output terminal to the power supply terminal. It is particularly advantageous to use exponential scaling of the conduction channel widths.

Abstract: In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).