Abstract: A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, whose output to a common data bus line can be "high" ("1"), "low" ("0"), or of very high impedance ("floating"). Each NOR-gate contains a low .beta. ("load") depletion mode type of MOS transistor and a high .beta. ("driver") enhancement mode type of MOS; the output load device contains an output driver enhancement mode type of MOS transistor and an output load MOS transistor having a threshold intermediate that of the depletion mode and enhancement mode type of MOS transistor. In this manner, only a single voltage source V.sub.DD, or typically about +5 volts in N-MOS integrated circuit technology is required to power the buffer circuit completely.

Abstract: An integrated circuit voltage reference (V.sub.REF) for MOS circuit utilization is supplied by the weighted difference amplification (30) of the voltages (V.sub.1, V.sub.1 ') developed by a pair of separate similar networks (10, 10' or 100, 100') each of which comprises a base-emitter junction of a bipolar semiconductor transistor (T.sub.1) whose emitter is connected to a first clocked voltage source (C.sub.1, C.sub.2, M.sub.1, M.sub.2) in a feedback loop of a difference amplifier (A.sub.1) and whose collector is connected to receive output of a second clocked voltage source (C.sub.3, C.sub.4, M.sub.3, M.sub.4) and to deliver output to a first input terminal of the difference amplifier (A.sub.1). In a preferred embodiment, a second input terminal of the difference amplifier (A.sub.1) is supplied by the output voltage of an auxiliary voltage source (C.sub.5, C.sub.6, M.sub.6, M.sub.7, M.sub.8, M.sub.9) which is in another feedback loop of this amplifier (A.sub.1).

Abstract: A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals.

Abstract: This invention furnishes a minimum geometry integrated circuit arrangement of flip-flop detectors for a random access memory array in MOS (metal oxide semiconductor) technology. By "minimum geometry" is meant that these flip-flops occupy no more lateral space than the memory cells occupy even when every cell is built within a lateral space of only twice the minimum feature size, that is, a space of twice the minimum width of a metallization line.

Abstract: A method for simultaneously patterning-over field oxide, gate oxide, and sidewall oxide--high conductivity metal-silicide electrode metallization for semiconductor integrated circuits involves (1) formation of an unpatterned polycrystalline silicon (polysilicon) layer everywhere on the exposed surface of all the oxides, (2) formation of a patterned photoresist layer on the polysilicon layer, (3) deposition of a layer of the metal-silicide over all exposed surfaces, (4) removal of the patterned photoresist layer to lift off metal-silicide, and (5) oxidation of only exposed portions of the polysilicon layer to form silicon dioxide. The polysilicon layer can be originally doped, so that the doped silicon dioxide can then be removed (without removing undoped silicon dioxide) by means of an etchant which attacks the dopant.

Abstract: Each of a pair of PN junction diodes (D.sub.1 ; D.sub.2) is separately dynamically biased by a different clocked current source arrangement (C.sub.1, M.sub.2 ; C.sub.2, M.sub.5). The resulting diode voltage drops (V.sub.1 and V.sub.2) are fed through a weighted difference amplifier (A; C.sub.3, C.sub.4, C.sub.5, C.sub.6) to produce a voltage reference V.sub.OUT which is relatively insensitive to temperature variations of the semiconductor body in which the PN junction diodes are integrated.

Abstract: In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2).

Abstract: An input differential amplifier stage (10), which feeds an output stage (20), has a feedback loop originating at a node (N.sub.1) in one branch, for controlling the current-source transistor (M.sub.5) of that stage. The feedback loop is characterized by a direct connection to the gate electrode of a transistor (M.sub.8) which drives the output stage (20), while the output at another node (N.sub.2), in the other branch of the differential amplifier stage (10) is fed to another transistor (M.sub.9) which also drives the output stage (20).

Abstract: A silicon device can be made more resistant to the destructive effects of ionizing radiation by a double annealing; the first annealing to a temperature of the order of 400 degrees C. in hydrogen, the second annealing also to a temperature of 400 degrees C. at a time when the device is not sealed against escape of hydrogen.

Abstract: In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

Abstract: In the patterning of an organic layer on a VLSI wafer by means of reactive oxygen (or other) ion anisotropic etching, build-ups of oxides (or other compounds) on the sidewalls of apertures formed in the organic layer are removed prior to etching the material, typically aluminum, of the VLSI wafer located at the bottom of these apertures, using the patterned organic layer as an etch mask.

Abstract: A feedback control arrangement in a fiber optic lightwave transmitter compensates for changes in the average power coupled from a laser into a fiber due to certain displacements of the fiber relative to the laser. The arrangement includes a laser (10) and an optical fiber (28) having a beveled end face (30) oriented to couple a major portion (13) of the laser beam into the fiber. The position of the fiber relative to the beam axis (12) is sensed by a pair of photodetectors (20, 22) positioned on opposite sides of the beam axis so as to receive other portions of the beam (15, 17) not coupled into the fiber. A feedback circuit (24) is selectively responsive to the smaller of the photodetector outputs for controlling the drive current to the laser so as to maintain the average power coupled into the fiber essentially constant.

Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Abstract: An array of semiconductor circuits integrated in a single semiconductor body substrate, each circuit having a separate input terminal, is protected from overvoltages in the inputs by means of a separate diode for each such circuit connected between its protected input node and a reference terminal (V.sub.DD) in common with all the other circuits. In addition, the high current path of a single auxiliary transistor is arranged to provide, in the presence of overvoltages, a low resistance path between the reference terminal (V.sub.DD) and the wide area substrate contact V.sub.SS in order to protect the input nodes in case of overvoltages when reference terminal (V.sub.DD) is disconnected ("floating").

Abstract: This invention involves a capacitor memory cell (C.sub.S) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T.sub.1), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) transistors (T.sub.2, T.sub.3) connected between the MOS capacitor and an A.C. refresh line which is independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor.

Abstract: A voltage multiplier circuit, in MOS technology, is arranged whereby MOS capacitors are alternately connected together in parallel (charging phase) and series (multiplying phase). Each capacitor is provided with a separate input MOS transistor as well as a separate feedback loop from the output side of each capacitor to the gate electrode of its input MOS transistor. During the multiplying phase, each input transistor is turned "on" in response to the voltage supplied by each feedback loop, thereby connecting the capacitors in series.

Abstract: In the fabrication of semiconductor integrated circuits which include recessed oxide isolation regions (29), formation of the undesired "bird's head" and "bird's beak" is avoided by reducing the rate of oxide growth from the sidewalls of isotropically etched recesses (22) while oxide is being grown from the bottoms of the recess regions. A silicon nitride mask (24) formed selectively on each of the sidewalls which has previously been coated with a thin silicon dioxide layer (23) reduces the rate of oxide growth therefrom, so that the oxidized recess regions have substantially planar surfaces after termination of the oxide growth.

Abstract: A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13.6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13.6) in order to tailor its conductivity profile.

Abstract: A filter in the form of a semiconductor charge coupled device (CCD) split electrode transveral filter section (10) of many transfer stages, typically of the order of 150, is characterized by a controllable detection threshold level by means of the addition of an auxiliary CCD split-electrode section (20) of but a few stages, typically one or two. Each segment of a split-electrode 209 of this auxiliary section (20) is connected to the corresponding sense line of the transveral filter section (10).

Abstract: A three-dimensional photographic system includes a source of pulsed-optical radiation characterized by an output optical pulse of risetime length less than the depth resolution desired of an object to be photographed. The pulse is directed on the object; the reflected radiation from the object is collected by an array of optical lenslets (lenticular plate), which forms a corresponding array of images of the object. This array of images is streaked, for example, by a streaking image converter tube, to form a corresponding array of streaked images in accordance with the said array of images of the object as a function of time. The array of streaked images is then recorded by a photographic film camera on other recording means; the recorded film can then be analyzed or viewed with human eyes for the purpose of three-dimensional analysis or viewing of the object.