Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.

Abstract: An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Abstract: In one method, a processor comprises both a speculative register file to store speculative register values and an architectural register file to store architectural register values. An output of the architectural register file is coupled to an input of the speculative register file to update the speculative register file when a misspeculation is detected.

Abstract: In one method, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

Abstract: In one method, a predicted predicate value may be determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

Abstract: An input-output (I-O) buffer for an integrated circuit. The buffer includes a controller and first and second groups of transistors to pull the node up and down, respectively. The controller is configured to turn on a transistor from the first group to drive a high bit on the node during a first period of time. The controller is further configured to turn on transistors from both the first and second groups, simultaneously, to terminate the node during a second period of time.

Abstract: A system includes a power supply, a meter coupled to the power supply, and a controller. The meter takes a measurement of a parameter that is approximately proportional to the power consumed from the power supply by at least a portion of a computer system. This parameter may include, for example, the current or voltage between the power supply and the portion of the computer system, or the duty cycle of a switching signal in the power supply. This measurement is then used by the controller to determine if the power consumed by the portion of the computer system reaches a threshold, and if so, the controller sends a throttle signal. A system and method such as this may be found useful to reduce the risk of a computer system blowing a fuse or tripping a circuit breaker.

Abstract: A processor comprises a processing core integrated on the same chip with a temperature sensing diode. The two terminals of the diode are coupled to each of two I-O ports of the processor. In accordance with one embodiment of the present invention, the electrical characteristics across the I-O ports are measured by an external control circuit to calculate a temperature of the processor. This temperature is compared to a threshold, and either an overtemp or undertemp signal is transmitted via a control line.

Abstract: In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

Abstract: Performing hazard detection in a processor that exhibits register latencies between execution units. The opcode classes of producer and consumer instructions are determined. Using these opcode classes, the register latency between the producer and consumer instructions is determined, and a register status signal is sent.

Abstract: A printed circuit board (PCB) includes a plurality of electronic devices electrically coupled together and disposed on a first side of the PCB. The PCB also includes a rail that is connected to the underside of the PCB. This rail is configured to cooperatively engage a rail guide connected to the chassis of the computer system such that the rail guide holds the rail and the PCB to the chassis, and the PCB and rail can slide with respect to the chassis.

Abstract: An input-output (I-O) buffer for an I-O node of an integrated circuit. The buffer includes a group of transistors to pull the node up. A shift register has each of two or more of its storage cells coupled to a gate of each of the transistors to control the impedance of the buffer.

Abstract: A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection.

Abstract: A method and apparatus for managing a memory region that stores locked and unlocked data. Data stored in the memory region is accessed. The data has an associated index that is stored in a locked index queue. While the index is stored in the locked index queue, the data is locked.

Abstract: Performing hazard detection in the presence of predication. The status of a consumer register associated with a consumer instruction is determined. The status and value of a predicate associated with the consumer instruction is also determined. A hazard signal is then sent based the status of the consumer register, the status of the predicate, and the value of the predicate.

Abstract: A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.

Abstract: A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.

Abstract: A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed in it by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, eletrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures.

Abstract: A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.