Abstract: A method and apparatus for storing, locking, and unlocking data in a memory array. The memory array includes a first line to store a first type of data while the first line is unlocked during a first period of time and to store a second type of data while the first line is locked during a subsequent second period of time. The memory array further includes a second line to store the second type of data while the second line is locked during the first period of time and to store the first type of data while the second line is unlocked during the second period of time.

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.

Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

Abstract: A film primarily comprising silicon crystal grains having a random crystal structure. The average size of the grains is within the range of approximately 50 .ANG. to 500 .ANG..

Abstract: Performing hazard detection using status and mask vectors. Predicate status and mask vectors are generated. From the predicate status vector it is determined if a predicate is pending, and from the predicate mask vector it is determined if the predicate is needed.

Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

Abstract: A circuit including a multiplexer and a comparator. The multiplexer has one input coupled to a portion of an odd result address bus and another input coupled to a portion of an even result address bus. The control input of the multiplexer is coupled to a least significant bit line of a source address bus. The output of the multiplexer is coupled to one input of the comparator, and the other input is coupled to a portion of the source address bus.

Abstract: A NRU algorithm is used to track lines in each region of a memory array such that the corresponding NRU bits are reset on a region-by-region basis. That is, the NRU bits of one region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Similarly, the NRU bits of another region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Resetting the NRU bits in one region, however, does not affect the NRU bits in another region. A LRU algorithm is used to track the regions of the array such that each region has a single corresponding entry in a LRU table. That is, all the lines in a single region collectively correspond to a single LRU entry. A region is elevated to most recently used status in the LRU table once the NRU bits of the region are reset.

Abstract: A method and apparatus for providing one of two clock signals to a processor based on a reference signal. An electronic component includes a processor, a first clock source configured to provide a first clock signal, an interface for receiving a second clock signal, and a reference signal line. The first clock signal is applied to the processor if a first reference signal is applied to the reference signal line, and the second clock signal is applied to the processor if a second reference signal is applied to the reference signal line.

Abstract: A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.

Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

Abstract: A decoupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate comprising electronic circuitry, and not over a second region of the substrate. The capacitor comprises a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer, and the capacitor provides capacitance for the electronic circuitry.

Abstract: A printed circuit board to support an integrated circuit and provide thermal dissipation. A layer of thermally conductive material is disposed between lower and upper dielectric layers. Above this structure is disposed another layer of thermally conductive material to be thermally coupled to an integrated circuit. A thermal via couples the two layers of thermally conductive material to each other.

Abstract: A method and apparatus for upgrading a computer system from one processor generation to another processor generation. The processor and its corresponding primary bridge are included together on the same circuit board. The circuit board has an interface which can be inserted into a socket of a system. The interface socket includes the memory bus and peripheral component bus from the bridge.

Abstract: A method and apparatus for indicating when a device in a computer system is communicating with memory. Information is communicated between the device and memory in a manner that bypasses a bus. A side-band signal that indicates that this communication is transpiring is sent to a second device connected to the second bus. In response to this side-band signal, a bit in a register of the second device is set to a value that is then communicated by way of the second bus.

Abstract: A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

Abstract: An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.

Abstract: A lid that provides thermal dissipation for an integrated circuit. The lid is designed to be fastened to a printed circuit board and includes a casing having thermally conductive upper and lower plates. Between the upper and lower plates, inside the casing, is a hollow interior region within which vaporizing fluid and two or more segments of wick reside.

Abstract: A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed in it by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, electrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures.

Abstract: A method and apparatus for regulating a voltage supplied by a power supply to an integrated circuit. A signal is sent to the power supply. This signal signifies that a change in the current drawn by the integrated circuit from the power supply will occur. Next, the voltage supplied by the power supply to the integrated circuit is adjusted in response to this signal before the change in current occurs. The adjustment is in a direction that will compensate for the anticipated voltage transient that will result from the change in the current.