Abstract: Techniques are disclosed for permitting low power operation of a signal processing circuit, such as a mixed signal processing circuit, by operating devices of the digital signal processing side at an energy-delay minimum. To permit this to occur, the negative logic supply rail of the digital signal processing circuit is operated at a negative potential. This negative potential is generated using a charge pump on an integrated circuit chip which can be also used to create a negative substrate potential. A positive logic supply rail can be generated using a DC to DC converter or voltage regulator. The potential of the positive logic supply rail can be negative, as long at it is more positive than the potential of the negative logic supply rail.

Abstract: A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Abstract: A front end for capturing seismic signals uses a voltage doubling circuit and an analog to digital converter (ADC) having different power levels available during respective operational phases. Power available the ADC is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected for the ADC to reduce power consumption for a delta sigma modulator used in the ADC and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Abstract: A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: DOS application programs are accommodated when using a controllerless modem by providing a virtual device driver. The virtual device driver emulates UART to UART communications and handles interrupts by the DOS applications and by a hardware port managed by the controllerless modem. In one implementation, the virtual device driver shares a communications interface in common with 32-bit applications. In a communication system environment, DOS applications can participate in modem to modem communications with remote DTEs and with other devices using the services of the virtual device driver.

Abstract: A video controller for controlling at least two video displays incorporates a video memory for storing first and second video frames of interleaved pixel data. A video memory controller connected to the video memory sequentially reads data for a first pixel from the first video frame and data for a second pixel from the second video frame. Each pixel data is in turn transferred to a look-up table connected to the video memory controller which converts the first and second pixel data to first and second display data. A selector coupled to the look-up table alternately routes the first display data to one video display and routes the second display data to the other video display.

Abstract: A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Abstract: An image displayed on a digital display such as a flat panel display is rotated while the same image is displayed on a cathode ray tube display in unrotated form. When image rotation is selected, the read address sequence into a frame buffer may be reversed and the bit read sequence may be reversed. Thus a frame of panel pixel data stored within the frame buffer of an external video memory may be scanned onto a flat panel to display a rotated image.

Abstract: A method and apparatus are used to continuously convert a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information for controlling the ADC components to produce a digital sample of the analog signal on the specified physical channel. At least one looping bit and at least one depth bit are also stored in a register on the serial port. The depth bit indicates a number of logical channels in one data scan. At least that number of logical channels are stored in the register. In response to a command bit indicating conversion mode, a quantity of data scans is output on a serial output pin of the serial port interface.

Abstract: An extended V.8bis command sequence enables a DTE to configure a DCE for alternative configurations and for independent V.8bis protocol negotiations. The DCE can be configured by sending it an AT command sequence as part of an initialization string. In this way, legacy applications can use the full capabilities of modems without rewriting the legacy application code.

Abstract: A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.

Abstract: A portable radio telephone handset operates as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the handset. The handset distinguishes between paging signals indicating CDPD mode communications and those indicating analog cellular communications. The handset also automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. The handset maintains an active status on a CDPD communication channel during a "sleep mode", when the handset can carry out AMPS activity.

Abstract: A V.34 compliant modem uses a noise whitening filter to compensate for noise enhancement in an equalizer. The noise whitening filter uses a 3 tap FIR the response of which is determined by 3 coefficients. The coefficients are derived using a newly developed extension of the Levinson-Durbin algorithm to complex numbers. The coefficients thus derived are used to control the precoder as well as the noise whitening filter. The coefficients are also used to control precoding reconstruction after the decoder.

Abstract: A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A digital to analog converter converts an N-bit digital signal into an M-bit digital signal and provides the M-bit digital signal to a conversion circuit which converts the M-bit signal to an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. An interpolation filter is used to increase the apparent sampling rate of the incoming N-bit signal.

Abstract: A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.

Abstract: A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.

Abstract: A 1-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.