Abstract: Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.

Abstract: An arrangement and method for adjusting the brightness of an image signal having digital pixel values to produce brightness adjusted output pixel values is provided with an adder and lower and upper clamp circuits. The adder adds a brightness value to the digital pixel values of the image signal to produce adjusted pixel values and a carry-out signal. The lower clamp circuit clamps the adjusted pixel values to a lowest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values below the lowest output pixel value. The upper clamp circuit clamps the adjusted pixel values to a highest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values above the highest output pixel value.

Abstract: A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers.

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract: Competition between subscriber stations attempting to access reverse channels in response to Temporary Equipment Identifier (TEI) messages is limited by requiring the subscriber stations to wait for a predetermined amount of time. The time delay is selected on the basis of a random number and a factor based upon the number of TEI messages broadcast. The method for determining response opportunities for subscriber stations also includes a back-off phase at the first stage. The time delays to the defer phase is based upon a random period of time and a predetermined maximum based upon the time needed for the microslots containing a TEI message.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.

Abstract: Interrupts are prioritized such that selected interrupts use shadow registers to save the current state of the machine, whereas other interrupts use a software implemented interrupt service routine (ISR) to save and restore the current machine state. Hence, the number of nested interrupts that can be serviced will not be limited to the depth of register shadowing.