Patents Represented by Attorney, Agent or Law Firm David N. Lathrop, Esq.
  • Patent number: 6640086
    Abstract: Using an apparatus like a cellular telephone, an operator is able to create a message by singing into the apparatus or by pressing buttons on the apparatus as he listens to background music presented by the apparatus. By pressing buttons, the operator is able to generate sounds as if he was playing a musical instrument. A remote server stores a representation of the operator vocal or tactile input, and sends a message to one or more recipients that renders the operator input and background music in a manner that substantially preserves the temporal relationship originally observed by the operator.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: October 28, 2003
    Inventor: Corbett Wall
  • Patent number: 6625343
    Abstract: In an optical switch which has a stationary electrode plate 23, a substrate 10, a movable electrode plate 20 formed integral with the substrate 10 through flexure portions 21, and mirrors formed on the top of the movable electrode plate 20 and which performs switching control of light by electrostatic driving of the movable electrode plate 20, an output optical fiber 334 and an input optical fiber 35 are arranged along two parallel straight lines, respectively, and mirrors 41 and 42 are formed on the movable electrode plate 20 in opposing relation to the output optical fiber 34 and the input optical fiber 35, respectively.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 23, 2003
    Assignee: Japan Aviation Electronics Industry Limited
    Inventor: Yoshichika Kato
  • Patent number: 6621860
    Abstract: There is provided an apparatus for and a method of measuring a jitter wherein a clock waveform XC(t) is transformed into an analytic signal using Hilbert transform and a varying term &Dgr;&phgr;(t) of an instantaneous phase of this analytic signal is estimated.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: September 16, 2003
    Inventors: Takahiro Yamaguchi, Masahiro Ishida, Mani Soma
  • Patent number: 6622085
    Abstract: An object of the present invention is to accomplish the automatic preparation of road data in which roads and intersections are expressed by polygons that show accurate agreement with the complicated road shapes on city maps. In simple polygon preparation processing 3, the respective line segments of road network data 2 in which roads are expressed as line segments are expanded in the direction of the width dimension, thus producing simple road polygon data 4 which has a width that is slightly greater than the width of the roads in the city map data 5. Next, in scissors data preparation processing 6, scissors data 7 which defines the outlines of roads is prepared from the city map data 5 by connecting shape lines in the vicinity of roads. Next, in road polygon preparation processing 9, road polygon data 9 which shows good agreement with the shapes of roads in the city map data is prepared by trimming the simple road polygons along the road outlines defined by the scissors data.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: September 16, 2003
    Assignees: Hitachi Software Engineering Co., Ltd., Kabushiki Kaisha Zenrin
    Inventors: Junya Amita, Yaheiji Hattori, Hiroki Kobayashi, Kiyonari Kishikawa
  • Patent number: 6611212
    Abstract: In one aspect of the invention, a stream is divided into two substreams, the first substream providing information relating to a ‘downmix’ signal obtained by matrixing and containing fewer channels than an original multichannel digital signal, and the second substream providing additional information allowing the original multichannel digital signal to be losslessly recovered by a decoder. In a preferred implementation, an encoder furnishes the downmix signal using a cascade of one or more primitive matrix quantizers, each of which implements an n-by-n matrix, followed by selection of the m channels required for the downnix. In a second aspect, a lossless compression system includes a dither seed in the encoded bitstream. The dither seed is used to synchronize a pseudo-random sequence generator in the decoder with a functionally identical generator in an encoder.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: August 26, 2003
    Assignee: Dolby Laboratories Licensing Corp.
    Inventors: Peter Graham Craven, Malcolm James Law, John Robert Stuart
  • Patent number: 6603591
    Abstract: On the top of a central protrusion 81 of a stationary electrode substrate 80 there is formed a stationary electrode 84A. A movable electrode plate 12 is supported at both sides thereof to a support frame 10 through flexures 19 and anchor parts 11. The movable electrode plate 12 is held displaceable vertically to the stationary electrode 12. The marginal edge of the protrusion 81 merges into a sloping face, on which an auxiliary electrode 84B is formed. In the case of separating the movable electrode plate 12 from the stationary electrode 84a, a voltage is applied between them.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: August 5, 2003
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventor: Keiichi Mori
  • Patent number: 6603595
    Abstract: An optical amplifier with a flattened wideband response is obtained by coupling counter-propagating pumping energy into an optical waveguide to cause Raman amplification in the optical waveguide, and by reflecting an amplified signal received from the optical waveguide into an output waveguide using a reflector having a spectral characteristic that is complementary to the spectral gain characteristic of the Raman amplification.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 5, 2003
    Assignee: JDS Uniphase Corporation
    Inventors: David F. Welch, Robert J. Lang, Edward C. Vail, Mehrdad Ziari
  • Patent number: 6601204
    Abstract: After initializing a Direct Rambus DRAM under test with initialization data, an address, pattern data and mask data are provided to the memory to effect therein a byte-wise masked write of the pattern data, and parallel mask data is converted to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating means. Based on the bit logical value of each serial mask data, it is decided whether data of each byte is write-enabled or not in the byte-wise masked write, based on the bit logical value of each serial mask data and either one of the initialization data and the byte-wise masked written pattern data is selected to generate expectation data.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: July 29, 2003
    Assignee: Advantest Corporation
    Inventor: Masaru Tsuto
  • Patent number: 6598004
    Abstract: A signal under measurement is converted into a digital signal by an AD converter, and a band-pass filtering process is applied to the digital signal to take out only components around a fundamental frequency of the signal under measurement. A data around a zero-crossing of the components around the fundamental frequency is interpolated to estimate a timing close to a zero-crossing point. A difference between adjacent timings in the estimated zero-crossing timing sequence is calculated to obtain an instantaneous period data sequence. A period jitter is obtained from the instantaneous period data sequence.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: July 22, 2003
    Assignee: Advantest Corporation
    Inventors: Masahiro Ishida, Takahiro Yamaguchi, Mani Soma
  • Patent number: 6594595
    Abstract: Timing jitter sequences &Dgr;&phgr;j[n] and &Dgr;&phgr;k[n] of respective clock signals under measurement xj(t) and xk(t) are obtained, and a covariance &sgr;tj,tk=(1/N)&Sgr;i=1N&Dgr;&phgr;j[i]·&Dgr;&phgr;k[i] is obtained. In addition, root-mean-square values &sgr;tj and &sgr;tk of the respective &Dgr;&phgr;j[n] and &Dgr;&phgr;k[n] are obtained, and a cross-correlation coefficient &rgr;=&sgr;tj,tk/(&sgr;tj·&sgr;tk) between the xj(t) and xk(t) is calculated.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: July 15, 2003
    Assignees: Advantest Corporation
    Inventors: Takahiro Yamaguchi, Masahiro Ishida, Mani Soma
  • Patent number: 6594788
    Abstract: A method of analyzing a repair of failure memory cell in a memory is provided, which is capable of searching a must-repair of a memory at high speed and of performing a simulation process for relieving a must-repair at high speed at the time point when it has been detected. There are provided a row address failure number counter/memory for counting the number of failure memory cells on each row address in the row address direction and storing it and a column address failure number counter/memory for counting the number of failure memory cells on each column address in the column address direction and storing it. The stored value in either one counter/memory is read out and the number of failure memory cells on each address is compared with the number of spare lines.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: July 15, 2003
    Assignee: Advantest Corporation
    Inventor: Takahiro Yasui
  • Patent number: 6590479
    Abstract: The invention allows for testing by high velocity signals of high density LSIs prior to being packaged having an electrode spacing on the odder of 150 &mgr;m, for example. Coaxial transmission lines 13 for termination formed through a terminal support 11 are arranged in a two-dimensional array. Connected to one ends of the transmission lines 13 are one ends of contact pins 18 such as conductive whiskers while the other ends of the transmission lines 13 are connected to a transmission line block 61 of a three-dimensionally upwardly gradually broadening configuration through a connection plate 72 similar in construction to the terminal support 11. The transmission line block 61 holds high frequency transmission lines 62 for relay connected at one ends to the other ends of the coaxial transmission lines 13 and having spacings between the adjacent lines broadened at the other upper ends. The widely spaced upper ends of the transmission lines 62 are connected to a performance board (not shown).
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: July 8, 2003
    Assignee: Advantest Corporation
    Inventors: Haruo Yoshida, Yasuhiro Maeda, Yoshihide Miyagawa
  • Patent number: 6588947
    Abstract: There is provided an optical connector adapted to be used as an optical input terminal or optical output terminal. A plug guide hole passing through a generally square-shaped insulation body is formed. An element folder for accommodating an optical element is made of a sheet metal. The element holder comprises a top plate, opposed side plates and a rear plate covering the top surface, the opposed side surfaces and the rear surface of the optical element mounted in the element holder, and a size between the inner surfaces of the opposed side plates is set to a value substantially equal to the maximum value of the corresponding external size of the optical element.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 8, 2003
    Assignee: Hosiden Corporation
    Inventors: Keiji Mine, Hiroshi Nakagawa, Yoshiaki Ohbayashi
  • Patent number: 6586953
    Abstract: An IC testing apparatus has a mainframe that includes a waveform generator, logic comparator, optical signal converter and photodector, and has a test head that includes an optical driver and optical output type voltage sensor. The optical signal converter converts a test pattern signal from the waveform generator into an optical signal that is sent to the test head through an optical waveguide to the optical driver. The optical driver converts the optical signal into an electric signal, which is applied to an IC under test in the test head. The optical output type voltage sensor converts a response signal received from the IC under test into an optical signal that is sent through an optical waveguide to the photodector, which converts it into an electrical signal for the logic comparator to compare so that the IC response can be assessed.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: July 1, 2003
    Assignee: Advantest Corporation
    Inventor: Toshiyuki Okayasu
  • Patent number: 6586924
    Abstract: A timing correcting method for correcting the timings of an IC tester at low cost, wherein the method uses a probe (300) for taking out a signal fed to a pin out of the pins of an IC socket (203) to which an IC to be measured is plugged when the probe is brought into contact with the pin and supplying a correcting pulse to the pin, and the timing of the correcting pulse taken in by a reference comparator (CP-RF) provided in the probe and the timing of a reference correcting pulse applied to an IC socket from a reference driver (DR-RF) provided in the probe are measured by a timing measuring function that the IC tester has, thus performing timing correction.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: July 1, 2003
    Assignee: Advantest Corporation
    Inventors: Toshiyuki Okayasu, Nobusuke Seki
  • Patent number: 6586689
    Abstract: In a multi-direction switch which is provided with a central switch and peripheral switches arranged about it and in which a keytop (40) is pressed to actuate a desired one of the switches, arms (52) of a pusher (50) are fixed to the underside of the keytop (40) with a central plate portion (71) of a frame (70) held between the the underside of the keytop (40) and the base (51) of the pusher (50) to provide therebetween a gap (4G) in which the keytop (40) is pivotable relative to the frame (70).
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: July 1, 2003
    Assignee: Japan Aviation Electronics Industry Limited
    Inventor: Michihiro Kuriyama
  • Patent number: 6574579
    Abstract: A waveform generating apparatus capable of outputting a desired waveform is provided. Among delay data is selected a set pulse generating delay data depending on test logical data and waveform mode information. The delay data, a skew adjusting delay data, and a fraction data in each test cycle are computed to obtain an integer delay data and a fraction delay data, which are supplied to a counter delay circuit. From the counter delay circuit are outputted a set pulse generating effective flag for delaying a test period timing by a delay time corresponding to the integer delay data, and a fraction delay data related thereto. The effective flag is delayed based on the related fraction delay data to obtain a set pulse. Similarly with the set pulse, a reset pulse is obtained, thereby to set/reset an S-R flip-flop to output a desired waveform.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 3, 2003
    Assignee: Advantest Corporation
    Inventor: Naoyoshi Watanabe
  • Patent number: 6560002
    Abstract: An optical switch that any vibration or oscillation transmitted to the optical switch from the outside is substantially prevented from being transmitted to a movable electrode is provided. In an optical switch comprising: a stationary electrode; a movable electrode opposed to the stationary electrode with a predetermined space therebetween; and a mirror mounted to the movable electrode, wherein the movable electrode and the mirror are moved together by applying a voltage between the stationary electrode and the movable electrode thereby to switch the path of an incident optical signal to the optical switch, a buffer member provided with a diaphragm is attached to the bottom of the stationary electrode, and a vibration or oscillation is substantially prevented from being transmitted to the movable electrode by the damping effects of the diaphragm and the space area formed above the diaphragm.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: May 6, 2003
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventor: Keiichi Mori
  • Patent number: D475076
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: May 27, 2003
    Inventor: Su-Fen Hou
  • Patent number: D475394
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 3, 2003
    Assignee: All-Logic Int. Co., Ltd.
    Inventor: Shun-Tien Yang