Abstract: A support plate having a top end edge defining a central convex portion which is the highest in the center thereof is vertically secured in the case to the bottom panel of the case, and a movable contact blade is supported on the top end edge of the support plate for rotating movement. Attached to the movable contact blade at one end thereof are two movable contacts spaced apart in the direction of the pivot axis of the blade. Two fixed contact blades are disposed on the bottom panel and each has a fixed contact attached thereto in opposition to a corresponding one of the movable contacts with the end portion of each fixed contact blade extending out through the bottom panel to define a terminal.

Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, TA3, - - - and the measured values T1, T2, T3, - - - become a constant value TC.

Abstract: A keyboard is severed along a boundary line between adjacent keytops located generally in the center of the length into keyboard parts (2, 3). An elongated cover plate (11) is pivotally attached on one side edge thereof to the lower portion of the severed face of one (2) of the divided keyboard parts, the cover plate (11) having opposed brackets (12) bent and extending in the same direction from the opposite ends thereof and opposed slide pins (19) provided one on each of the brackets toward the other side edge of the cover plate opposite from the severed face, the slide pins (19) being slidably received in corresponding elongated grooves (16) formed in the front and rear outside surfaces of the other divided keyboard part (3), and pins (17, 18) provided on the front and rear side panels of each of the divided keyboard parts being slidably and loosely fitted in elongated slots in moving links (13).

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories.

Abstract: In a computer system, the controller of one or more primary data recording devices sends update information to the controller of one or more secondary data recording devices to maintain a remote copy of data stored on the primary data recording devices. The primary controller receives a command from a computer that specifies a prospective suspend time after which remote copy operation is to be suspended. After the suspend time passes, the primary controller stops sending the update information to the secondary controller and begins storing indicators of the updated information in cache memory. The primary controller may resume remote copy operation in response to a command received from the computer by first entering into a pending mode of operation in which cached indicators are used to identify update information that must be sent to the secondary controller to resynchronize the remote copy. When the information for all cached indicators has been sent, normal remote copy operation may be resumed.

Abstract: Adjacent a side wall of a casing, a strap supporting post 49a is formed integrally with and extends form the inner surface of the top panel 41a of the upper casing half 41. The strap supporting post 49a has a screw bore 51 extending from the end face of the projecting end thereof and therethrough deep into the top panel 41a. A reentrant cavity 56 is formed in one side wall of the casing such that the post 49a is positioned generally in the center of the cavity. A metal-made screw 54 is passed through a through-bore in the lower casing half 42 and threaded into the screw bore to fasten the upper casing half 41 and the lower casing half 42 together. A strap is hooked on the post 49a by being inserted into the cavity from one side of the post 49a to wrap around the post and then being pulled out of the cavity from the opposite side of the post.

Abstract: A magnetic sensor switch is provided in which a magnetic sensor is responsive only when a magnet approaches it, to turn electrical contacts of the switch on and off. A cylindrical magnetic sensor having oppositely polarized magnetic poles at opposite ends thereof is mounted for rotation in clockwise and counter-clockwise directions. An auxiliary magnet is located in a region outside of the rotating radius of the magnetic sensor and in the vicinity of one magnetic pole of the magnetic sensor. The auxiliary magnet imparts a biasing force for holding the magnetic sensor at a position rotated through a predetermined angle. A movable contact piece is attached to the magnetic sensor and is adapted to be rotated as the magnetic sensor is rotated to thereby bring corresponding contact or contacts of the movable contact piece into contact with one of a pair of fixed contact pieces located in opposition to the contacts of the movable contact piece.

Abstract: A signal under measurement is transformed into a complex analytic signal using Hilbert transformation to estimate an instantaneous phase of the signal under measurement from the complex analytic signal. A zero-crossing timing sequence of the signal under measurement is estimated using the instantaneous phase. An instantaneous period sequence of the signal under measurement is estimated from the zero-crossing timing sequence to obtain a jitter of the signal under measurement from the instantaneous period sequence.

Abstract: A signal to be measured is waveform-formatted to a square waveform that retains the frequency, duty ratio and jitter component of the original signal, and the leading (or trailing) edge of the waveform-formatted output is sampled by a sampling clock of a frequency slightly different from 1/N of the frequency fM of the signal to be measured. The samples are converted by an A/D converter to digital data Vn(t), which is stored in a memory. The difference between the stored digital data Vn(t) and the rise-up characteristic line V′(t) is calculated to detect jitter J′n(t).

Abstract: A memory testing method and apparatus each capable of performing an erase test for a non-volatile memory in a short time are provided. In case of carrying out an erase test inspecting as to whether the storage data in each of the memory cells in a block to be tested of a non-volatile memory has been erased or not by an erasing operation, there are provided two failure address storage memories each storing therein addresses of failure memory cells. These failure address storage memories are alternately used to store therein only addresses of failure memory cells detected during the erase test. In the second time and the succeeding erase tests, the addresses of the failure memory cells stored in either one of the failure address storage memories in the preceding erase test are read out to access only the failure memory cells in the memory under test, thereby to inspect as to whether the storage data in each of the failure memory cells has been erased or not.

Abstract: A switch having a long contact life is provided. A neutral contact blade is provided with a first neutral contact and a second neutral contact. A primary movable contact blade and a secondary movable contact blade are supported by these first and second neutral contacts, respectively, for seesaw motion. The operation of a lever causes the primary movable contact blade and the secondary movable contact blade through a pushrod to move in a seesaw motion in such a manner that a secondary movable contact provided on one end of the secondary movable contact blade contacts with an associated secondary fixed contact before a primary movable contact provided on one end of the primary movable contact blade contacts with an associated primary fixed contact, whereas after the primary movable contact of the primary movable contact blade is separated from the primary fixed contact, the secondary movable contact of the secondary movable contact blade is separated from the secondary fixed contact.

Abstract: In a keyboard switch including a pantograph mechanism comprising a U-shaped link 14 having a pair of stud shafts 14C rotatably and movably supported in bearing portions 13B of a base 13 and a link 15 including a frame-like portion 15A and having a pair of stud shafts 15D rotatably supported in bearing portions 13C ofthe base 13, ribs 14F having tapered surfaces 14G are provided along the peripheral surfaces of bosses 14D defining the center of rotation of the link 14 while holes 15E in the link 15 for mating with the bosses 14D are formed with keyways 15F. When a force tending to pull the keytop up further from it returned original position is applied to the keytop, the tapered surfaces 14G and the angular edges of the keyways 15F are forced into contact with each other. This urging force in turn urges the opposed legs 14B of the link 14 to expand apart from each other in the directions indicated by the arrows 19, whereby the link 14 is prevented from dislodging from the base 13.

Abstract: The storage capacity of a failure analysis memory that performs an interleaved operation is reduced. There are provided a lower order address selecting part for selecting and extracting at least the least significant bit of an address signal, a bank control part for generating a bank switching signal by a logical signal outputted from the lower order address selecting part, a plurality of flip-flops for selecting either one of a plurality of banks operating in the interleaved operation by the bank switching signal outputted from the bank control part, and an access means for accessing an address of a memory constituting the selected bank by an address signal composed of the remaining higher order bit or bits of the address signal.

Abstract: There are provided an optical transfer characteristic measuring method and apparatus capable of measuring an optical transfer characteristic of an optical device on optical frequency axis in wide optical frequency bandwidth with high resolution. There are provided a variable wavelength sweep type light source capable of switching the wavelength of an optical signal generated therefrom stepwise and sweeping the optical frequency of the optical signal in a predetermined frequency range, and a variable wavelength reference light source capable of switching the wavelength of an optical signal generated therefrom stepwise and not capable of sweeping the optical frequency of the optical signal.

Abstract: A metal cover 21 is mounted on the rear end side of a body 11 to cover its top, both side surfaces and read end face, and the metal cover 21 has a pair of soldering portions 25, which are soldered to a circuit board so that the body 11 is pressed and fixed to the circuit board.

Abstract: A memory testing apparatus is provided, which can test in short time a memory having a block function like a flash memory. In addition to a failure analysis memory AFM capable of storing failures of all bits of a memory under test MUT, are provided a first bad block memory BBM and a second bad block memory CFM each having its storage capacity corresponding to the number of blocks that the memory under test has. The results of an initial test are stored in the first bad block memory. Utilizing the results of the initial test as mask data, bad blocks which have been determined to be failure in the initial test are masked by the mask data, respectively, so that a functional test for the bad blocks are omitted and the functional test for only pass blocks is performed. The results of the functional test are stored in the second bad block memory, and only the blocks having their bad block data stored in the second bad block memory are determined as to whether they are repairable or not.

Abstract: There are provided a timing calibration apparatus and a timing calibration method capable of carrying out the calibration of timing on an IC tester with high accuracy. There is provided a probe to be sequentially contacted with pins of an IC socket on which an IC under test is to be mounted, and a calibration pulse supplied to the IC socket from the IC tester is taken in the probe. The calibration pulse is compared with the reference timing, thereby to calibrate the timing on a driver included signal path. In the probe a calibration pulse is generated, which is sequentially supplied to the pins of the IC socket, thereby to calibrate the timing on a comparator included signal path in each of channels. There are provided in the probe an optical modulator for converting an electric signal into an optical signal and an optically driven type driver. An optical cable couples between a calibration controller provided in the IC tester and the probe.

Abstract: A housing and a bottom cover are secured together and have pairs of aligned through-apertures, and probe pins are accommodated in respective pairs of through-apertures to provide an IC socket. Each probe pin comprises a tube having a stop flange formed around its outer periphery, a movable plunger accommodated in the tube such that an extension portion of the movable plunger in urged to project out of a narrowed first end portion of the tube by a first coil spring, and a fixed plunger fitted to a second end portion of the tube. Each probe pin is urged by a second coil spring such that the stop flange on the tube is urged into abutment with a shoulder portion of a through-aperture of the bottom cover, whereby a tip end of the fixed plunger is projected beyond the outer surface of the bottom cover and a tip end of the movable plunger is projected beyond the outer surface of the housing.

Abstract: A transient power supply current testing technique which affords a high level of observability is used to prepare a list of detectable faults including a gate delay fault, an open fault and a path delay fault. A test pattern sequence formed by two or more test patterns is obtained (202), a train of transition signal values which occur on various signal lines within the circuit when the pattern sequence is applied to operate IC under test is determined by a transition simulation (203), and the train of transition signal values occurring on various signal lines is used to prepare a fault list which are detectable by the transient power supply current testing when the pattern sequence is used to operate the IC under test (204).