Abstract: A nonvolatile memory having a memory array including a plurality of data cells and a read circuit. The read circuit includes a plurality of sense amplifiers, each connected to a respective array branch to be connected to the data cells. The nonvolatile memory also includes a reference generating circuit including a single reference cell arranged outside the memory array and generates a reference signal. The reference generating circuit includes a plurality of reference branches, each connected to a respective sense amplifier, and circuits interposed between the reference cell and the reference branches to supply the reference branches with a signal based on the reference signal.

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: Driver and overload protection circuit for an electrical switch means. Switching control pulses with a minimum edge duration are fed to a two stage comparator circuit having first, lower and second, higher comparator threshold values. When the lower comparator threshold value is exceeded by a switching control pulse, the electrical switch means is rendered conducting. There is provided an overload detection circuit which, upon detection of overload of the electrical switch means, effects switching off of the same. For avoiding that turning on spikes upon each turning on of the electrical switch means, for example when switching capacitive loads, lead to deactivation of the switch means, any overload signal of the overload detector means is blocked as long as the instantaneous voltage value of the particular switching control pulse is not above the upper comparator threshold.

Abstract: A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

Abstract: A circuit for restoring bits transmitted by an asynchronous signal includes a first comparator for comparing the level of the asynchronous signal with a first threshold adjusted as a function of the output of the first comparator during synchronization bursts of the asynchronous signal, and at least a second comparator for comparing the level of the asynchronous signal with a second threshold correlated to the first threshold.

Abstract: An analog switch formed from a MOS transistor switch includes means for applying to the bulk terminal of the transistor switch the voltage of either one of the two main terminals of the transistor switch as a function of the relation between the voltages of said main terminals.

Abstract: A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

Abstract: A sensor of instantaneous power which is dissipated through a power transistor of the MOS type connected between the output terminal of a power stage and ground. It comprises a MOS transistor having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node which is coupled to the output terminal by means of a current mirror circuit which includes a resistive element in its input leg. Connected to the circuit node is the base terminal of a bipolar transistor which is respectively connected, through a diode and a constant current generator between the output terminal and ground.

Abstract: A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.

Abstract: A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor.

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract: The present invention relates to a power amplifier having an output stage in MOS technology, including an upper half-output stage comprised of two P-channel MOS power transistors mounted as a current mirror, a lower half-output stage comprised of two N-channel MOS power transistors mounted as a current mirror, an output terminal of the amplifier corresponding to the common drains of a first MOS transistor of the upper stage and of a first MOS transistor of the lower stage, and a control stage in bipolar technology for setting, according to a control voltage, two control currents of the half-output stages.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A device for protection against electrostatic discharges on the terminals of a MOS integrated circuit and characterized in that it consists of a first and a second circuit branch coupled between the terminal to be protected and ground. The first circuit branch has two field transistors. The gate of the first field-effect transistor is connected to terminal to be protected, and the gate of the second field-effect transistor is connected to a first resistance of the second circuit branch. The second circuit branch has a third field-effect transistor with its gate terminal connected to ground and a second resistance inserted between the third transistor and the terminal to be protected.

Abstract: A direct current boost converter which has a simple structure using only one coil, and which can apply a driving voltage to a capacitive load which reciprocates in polarity is discussed. A first direct current branch circuit composed of first and second transistors is connected in parallel to a second direct current branch circuit composed of the third and fourth transistors. A coil is connected between the intermediate nodes of the transistors of these direct current branch circuits, and these nodes are further connected to both terminals of an EL panel through first and second diodes. The nodes between the first and second diodes and the EL panel are grounded through fifth and sixth transistors, respectively. A clock signal is applied to the first and third transistors, and a gate signal with an opposing phase is applied to the second and fourth transistors.

Abstract: A method and a circuit generates a pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. The pulse synchronization signal is generated upon sensing a change in logic state on at least one of a plurality of address input terminals of the memory cells to also generate an equalization signal for a sense amplifier. The logic state of said pulse synchronization signal is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal. To this aim, a re-acknowledge circuit portion is provided which is input a corresponding signal to the equalization signal and feedback connected to the output node to drive the discharging of the node with a predetermined delay from the reception of the input signal.

Abstract: The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

Abstract: A speed sensor for a ship, more particularly, a thin speed sensor which can be mounted in the hull of the ship and remain flush with the outer surface of the hull. The transducer assembly for the speed sensor is composed of two thin piezoelectric transducers mounted in a spacer plate that locates them in an exact position relative to each other. A baseplate and a coverplate are affixed by appropriate adhesive techniques to each side of the transducers to create a single transducer assembly. Holes through the baseplate and spacer plate permit electrical contact to each side of the transducers so that they may be stimulated to generate acoustic waves. The entire transducer assembly is significantly thinner than the hulls of most watercraft. Thus, a large hole completely through the hull is not necessary. Rather, a shallow recess approximately equal to the thickness of the transducer assembly is made in the hull to countersink the transducer assembly flush with the hull.

Abstract: The present invention relates to a preamplifier including inputs for receiving input video signals representative of an image to be displayed on a screen, inputs for receiving logic signals representative of information to be displayed in superimposition on the screen, and outputs for supplying output video signals generated based on the input signals or the logic signals. An input receives a control signal to select which signals are used to generate the output video signals. In a first display mode, the signals used are the input signals, and in a second display mode, the signals used are the logic signals. Decoders and controllers allow monitoring of the state of the logic signals which select, in the second display mode, the input video signals to generate the output video signals.

Abstract: The present invention relates to a device for generating and regulating a gate voltage in an electrically programmable non-volatile memory with single power supply of the type comprising a voltage booster driven by a clock signal applied to a first input terminal thereof and having an output terminal on which is produced a signal with higher voltage. This device comprises a lower regulator block and a programming switching block inserted in parallel each other between said output terminal of the voltage booster and an output terminal of the gate voltage generating and regulating device with said lower regulator block being driven by a plurality of switching signals to supply on the output terminal of the device a plurality of regulated voltages and feed the control gates of the non-volatile memory cells.