Abstract: A switching power converter including a ring oscillator constructed using a plurality of series connected inverters is utilized to generate a plurality of waveforms. A selection circuit, in cooperation with an exclusive OR gate, produces an output signal from the exclusive OR gate having a duty cycle which can vary from 0 to a nearly 100% duty cycle, depending upon which waveform is selected. The output signal is utilized to control a switching power converter.

Abstract: An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: On a semiconductor wafer, recognition marks are fabricated on the crossing points of scribe lines for the purpose of proper wafer alignment in wafer sawing process. Since the recognition mark has a distinctive pattern that is distinguished from other circuit patterns on the chip, the recognition mark can be easily recognized by a camera in a sawing apparatus, and reduce the chance of wafer misaligning. When a part of circuit pattern on the semiconductor chip is used for the alignment purpose, the chance of wafer misalignment relatively high due to the similarity between the part chosen and other parts of the circuit pattern. The present invention also provides a method for sawing the wafer using the recognition marks.

Abstract: A multi in-line module and an electronic component socket for the multi in-line module are provided. One embodiment of a multi in-line memory module includes a printed circuit board having at least two protrusions formed along one edge of the printed circuit board. Each of the protrusions has first and second surfaces for blocks of contact pins. Accordingly, the module can include three or more pin blocks on separate surfaces of the protrusions. The module provides a large number of pins without being significantly larger than a conventional SIMM or DIMM. Alternatively, physical and electrical attachment of multiple circuit boards provides three or more independent pin blocks on the various surfaces of the printed circuit boards. A socket for a module includes dielectric protrusions with two or more gaps between the protrusions and contact pins on side surfaces of the protrusions that are in the gaps.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: Copolymers and terpolyers are used in chemically amplified resists. The terpolymers are of the formula: wherein R3 is selected from the group consisting of hydrogen and a C1 to C10 aliphatic hydrocarbon, wherein the aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof; R4 is selected from the group consisting of hydrogen and a C1 to C10 aliphatic hydrocarbon, wherein the aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof; R5 is selected from the group consisting of hydrogen and methyl; R6 is selected from the group consisting of t-butyl and tetrahydropyranyl; m and n are each integers; and wherein n/(m+n) ranges from about 0.1 to about 0.5.

Abstract: An apparatus for forming a film on a substrate includes a reaction chamber and gas supply lines. The gas supply lines supply gases for depositing and annealing the film. Depositing a dielectric film and annealing the dielectric film are performed in situ using the reaction chamber. Thus, the time required for forming the dielectric film is shortened, improving the productivity. Also, deposition and annealing of the dielectric film are performed in the same reaction chamber, so that less area is required for manufacturing equipment.

Abstract: Chemical-mechanical processing of a patterned substrate selectively etches patterned portions of the substrate surface, producing deep narrow features with a rapid etch rate. This chemical-mechanical processing is termed chemical-mechanical etching and produces a result that is substantially the opposite of the planarization that is achieved by conventional chemical-mechanical polishing (CMP). A chemical-mechanical polishing (CMP) technique which is widely used for planarization of surfaces is converted for usage as an etching technique, a chemical-mechanical etching (CME) technique, by forming a patterned mask on the substrate surface prior to mechanical polishing. The usage of chemical-mechanical polishing techniques in this manner yields an etching method with properties including a rapid etch rate, a highly controllable etch rate, a highly controllable etch depth, and a greatly selective etch directionality.

Abstract: Read and write performance in a magnetic thin-film head is improved by forming a highly compact multiple-gap head with separate magnetic core and coil structures for a read head and a write head that are respectively designed to improve reading and writing performance. A thin film magnetic head includes a thin-film magnetic core including a read core portion and an interconnected write core portion, a thin-film read coil encircling the read core portion, and a thin-film write coil encircling the write core portion. The read core portion is separated by a read magnetic gap and the write core portion being separated by a write magnetic gap. The read gap and write gap are mutually combined in close proximity in abutting sections of the read core portion and the write core portion respectively so that a magnetic medium is accessible to the read gap and the write gap simultaneously.

Abstract: A method for fabricating a semiconductor device reduces soft errors, thereby enhancing reliability of the semiconductor device. In the method, a benzo cyclo butene (BCB) layer having a low water intake rate and an excellent blocking effect against alpha particles is formed between an alpha particle source such as a solder ball and sensitive integrated circuit devices such as a memory cell.

Abstract: Automated equipment mounts heat sinks on printed circuit boards. First heat sinks, semiconductor modules and second heat sinks are consecutively seated on a plurality of built-up pads as the built-up pads move from station to station around a built-up pad conveyer. Rivets are mounted in a first heat sink and inserted through holes in a semiconductor module and a second heat sink when seating the semiconductor module and the second heat sink. Working the rivets fixes the first heat sink, the semiconductor module and the second heat sink permanently, and thereby forms a semiconductor product. After that, a label is attached on the semiconductor product and the riveting quality and the labeling quality of the semiconductor product are inspected.

Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.

Abstract: A method for efficiently optimizing the bin widths for a distribution or an image to be compressed. An image having symmetric uni-modal distribution is divided into a zero bin having a zero bin width and a plurality of outer bins having an outer bin width. M numbers of predetermined candidate values for the zero bin width and N numbers of predetermined candidate values for the outer bin width are provided. A zero bin probability is derived from an entropy function. The allowable zero bin width is calculated from the zero bin probability and target bit rate. The allowable zero bin width is then searched to obtain an optimum combination of the zero bin width and the outer bin width, the optimum combination being the combination having the least distortion measure. In one embodiment, a fast algorithm is used to search the outer bin width for each given zero bin width, reducing the required combination by a factor of logN/N.

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract: A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor substrate; multiple conductive structures formed on the top surface of the semiconductor substrate; self-aligned conductive pads filling spaces between adjacent conductive structures and between the isolation region and the conductive structures. The method includes: forming a conductive structure on a semiconductor substrate; forming insulating sidewall spacers on the conductive structures, forming a conductive layer that fills spaces between the conductive structures and contacts the semiconductor substrate; and patterning the conductive layer.

Abstract: A cable sleeve system for bone fixation, comprising a cable, and a sleeve including a head for securing the cable and a piercing portion, wherein the piercing portion projects from a bottom face of the head substantially perpendicularly therefrom, and the head is provided with a bore extending in parallel with the bottom face for securing the cable therein, the head being adapted to be crimped to secure the cable therein. Because the sleeve can be made highly compact, it is possible to avoid undesirable side effects such as hemorrhage and inflammation due to irritations to the human body tissues which occurred frequently in the case of the cable securing method using the conventional cable grip.

Abstract: A socket pin and a socket for electrical testing of a semiconductor package suppress electrical open/short defects due to contact failure and reduce manufacturing costs. The socket pin includes: an upper portion that connects to a lead of the semiconductor package, for exchanging a signal between the semiconductor package and a tester; a body connected to the upper portion, for buffering at two points, a downward force applied by the lead of the semiconductor package to the upper portion; a lower portion connected to the body of the socket pin, the lower portion being elastically durable to the force from the upper portion and the body; and a lower socket pin connected to the lower portion, which acts as a path for transmitting or receiving an electrical signal.

Abstract: A method of testing phase locked loops (PLL) and a testing circuit comprising the steps of applying a normal stimulus signal whose frequency is within the lock range of the PLL to the input of the PLL, substituting the normal input stimulus with an alternative signal derived from an internal feedback of the PLL, adding or deleting one or more cycles from the alternative signal and observing the response of the PLL to the alternative signal. Variations of the method allow for determining Gain-Bandwidth product, lock range, lock time, Bit Error Rate, Jitter and other parameters which can then be compared with predetermined values to determine whether the PLL is properly functional.