Abstract: A precharge circuit for a memory device includes a first precharge sub-circuit that precharges data input/output lines to a first level for a write operation, and a second precharge sub-circuit that precharges the data input/output lines to a second level higher than the first level for a read operation. Therefore, even when a power supply voltage of the semiconductor memory is low, the input/output lines are precharged to a sufficiently high voltage and an input/output sense amplifier can operate normally, thereby outputting correct data.

Abstract: A sense amplifier of a semiconductor memory device has increased driving capability and can reduce the size of a memory device. The sense amplifier includes a pull-up sense amplifier and a pull-down sense amplifier which are connected between a bit line and a complementary bit line to sense data stored in a memory cell, and a pull-up sense driver and a pull-down sense driver each of includes an NMOS transistor. The sense amplifier can reduce the sensing time between the pull-up and pull-down sense drivers starting to operate and a column select line being enabled. The sense amplifier also reduces the time necessary for restoring or refreshing the data or charge in the capacitor of a memory cell after the sensing operation.

Abstract: Disclosed is a method to reduce external signal interference with signals in a computer disk storage system including a disk drive. An electrically conductive housing is provided for the disk drive to enclose and support within the housing analog circuitry, a motor for rotating media for the storage of information, and circuitry for converting analog signals to digital signals. Circuitry and conductors which carry analog signals are enclosed within the electrically conductive housing and signal conversion circuitry is provided within the housing to convert analog signals into digital signals before transmission to the exterior of the housing.

Abstract: A dynamic random access memory device and a &mgr;BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a clock signal and includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The n data input pads respectively connect to the n input receivers and transfer the input data signals to the input receivers. The n input receivers are divided into x groups according to their positions, and the x reference voltage input pads respectively connect to the x groups of input receivers for commonly applying the reference voltage to the input receivers in the respective groups. Each reference voltage input pad can connect to its group of input receivers through one or multiple common lines. The package includes a first ball that receives the reference voltage.

Abstract: An ion implantation apparatus for use in manufacturing semiconductors includes a loopback device connected to a bias ring for a Faraday cup. The loopback device detects whether a current flows through the bias ring and generates an interlock signal to be supplied through an interface to a controller. In response to the interlock signal, the controller stops an implantation operation of the apparatus, and a driver circuit drives a warning device in response to the interlock signal.

Abstract: A memory device includes a plurality of memory banks, a plurality of data line pairs coupled to the memory banks, and an input/output (IO) sense amplifier shared by at least two neighboring memory banks. The IO sense amplifier includes a plurality of current sense amplifiers and a latch sense amplifier. Each current sense amplifier couples to and senses a corresponding data line pair. The latch sense amplifier selectively senses signals from the plurality of current sense amplifiers and generates an output signal at a suitable voltage for peripheral circuitry. Circuit area required for sense amplifiers is reduced because at least two memory banks share a latch sense amplifier, instead of having one latch sense amplifier for each memory bank.

Abstract: A flexible internal power supply voltage generating circuit of a semiconductor memory device includes a step-down circuit and a selection circuit. The selection circuit selects the step-down circuit for use when the semiconductor device uses a high external power supply voltage but bypasses the step-down circuit for a low external power supply voltage. One such circuit additionally includes a power supply terminal and a control circuit. The power supply terminal receives an external power supply voltage. The control circuit compares a feedback internal power supply voltage with a reference voltage at the time of driving a word line and then generates a control voltage signal for controlling a DIP of an internal power supply voltage caused by driving the word line. A selection circuit selectively connects a high voltage node or a low voltage node to the power supply terminal according to the external power supply voltage.

Abstract: Cut-off control circuits implementing DC-coupling and AC-coupling to CRT cathodes can employ the same preamplifier integrated circuits with few additional components. The preamplifier includes a switching unit for receiving control data, generating a control signal according to control data, and outputting the control signal internally or externally. The switching unit provides a control signal internally to an amplification circuit, when the preamplifier operates in a cut-off control circuit having a DC-coupling to a CRT. With a DC coupling the amplification circuit controls a DC bias applied to a CRT cathode. The switching unit provides a bus control signal externally to a bias circuit, when the preamplifier operates in a cut-off control circuit having an AC-coupling to a CRT.

Abstract: A semiconductor memory device such as a DRAM maintains uniform sensing efficiency of a data line sense amplifier The memory device includes multiple memory blocks, and each memory block containing bit line sense amplifies, load transistors, and switching transistors. The load transistors generate a current on the data lines when the respective memory block is selected for a read operation. The switching transistors connect the respective bit line sense amplifiers to data line pairs. The sizes of the load and switching transistors can adjust for different distances along data lines between the respective bit line sense amplifiers and data line sense amplifiers. Accordingly, the data line sense amplifiers have uniform sensing efficiency regardless of the transmission distance.

Abstract: A compact low-power radio frequency (RF) transceiver with a built-in antenna provides wireless communication between a computer and another device. A direct conversion receiver together with a voltage controlled oscillator, phase lock loop circuits, digitally controlled divider circuits and a patch antenna are packaged into a compact enclosure, having dimensions within the PCMCIA format. In some embodiments, the transceiver enters a sleep mode whenever it is idle in order to further conserve power. In other embodiments, a signature detector enables the transceiver to distinguish between noise and valid messages by recognizing a signature word embedded in the data packet.

Abstract: An input and output line equalizing circuit for connection to a pair of input and output lines of a memory device. The equalizing circuit includes an equalization control circuit providing at an output a precharge signal, and an equalizing unit connected to the input and output lines. The equalizing unit responding to receipt of a precharge signal from the equalization control circuit to maintain the pair of input and output lines at the same voltage level. The equalizing control circuit includes a first transmission gate and a second transmission gate.

Abstract: A capacitor of a semiconductor device includes a first insulating layer having a contact hole therethrough and a contact plug that is in the contact hole and electrically connected to a semiconductor substrate. Also, a diffusion barrier layer is on the contact plug and fills the contact hole, and a storage node is on the insulating layer in contact with the diffusion barrier layer. The storage node has a uniform outer surface morphology and a cavity therein. A second insulating layer is on the first insulating layer and separates the storage nodes from adjacent storage nodes, and a fill layer fills the cavities of the storage nodes. A dielectric layer having a large dielectric constant covers the second insulating layer, the fill layer, and the storage nodes, and a plate node is on the dielectric layer. The storage node has a smooth surface adjacent the dielectric layer, which decreases leakage current.

Abstract: A voltage boosting circuit of a semiconductor device is disclosed. The voltage boosting circuit includes a voltage detector, an active kicker controller, and an active kicker. The voltage detector generates a detection signal after the determining whether a potential of the signal to be boosted is higher than a boost voltage target level. The active kicker controller generates an active kicker control signal in response to the detection signal and the clock signal. The active kicker drives the signal to be boosted in response to the active kicker control signal. The voltage detector includes a current source, a number of switching devices, a current compensating circuit, and an inverter circuit. The current compensating circuit provides a compensating current proportional to a power supply voltage.

Abstract: A method of manufacturing a disk drive which includes a disk having first and second magnetic surfaces and first and second read/write transducers for writing information on and reading information from the magnetic surfaces. The method includes determining a track width performance characteristic to be measured for the read/write transducers, establishing ranges of values for the performance characteristic to define a plurality of performance groups. The performance characteristic is measured for a plurality of read/write transducers from which the first and second read/write transducers for the disk drive are to be selected and the read/write transducers are segregated into groups based on the performance characteristic value falling within the range of the group. The disk drive is assembled using read/write transducers from only one of the groups. The measurement of the performance characteristic is accomplished either electrically or optically.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.

Abstract: A method for automatically operating a robot, attached to a lawnmower or other unmanned machine, within an enclosed area is disclosed.

Abstract: A semiconductor memory device is capable of simultaneously driving multiple wordlines during wafer burn-in. The semiconductor memory device includes a wordline driving block, a predecoder, a row decoding block, and a burn-in controller. The row decoding block connects to the burn-in controller and the wordline driving block and generates a plurality of wordline enable signals for controlling the wordline driving block. The row decoding block includes a plurality of row decoders, each associated with multiple wordlines. For normal memory accesses, decoding units in the row decoders determine which of the row decoders are activated. In a wafer burn-in mode, the burn-in controller controls which or the row decoders are activated. Transistors in the decoding units can be sized for enabling single wordlines, and transistors in the burn-in controller can be sized for simultaneously enabling multiple wordlines.

Abstract: An apparatus in accordance with the present invention includes separate transporting units respectively for good and rejected semiconductor devices. As a result, respective handlings of the rejected and good devices, such as loading of the good devices into a burn-in board or an unloading tray and loading of the rejected devices into a rejecting tray, can be performed separately without interfering each other.

Abstract: A capacitor of a semiconductor device includes a first interlayer dielectric film pattern formed on a semiconductor substrate and having a first contact hole therein and a contact plug buried in the first contact hole and electrically connected to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion barrier layer pattern for preventing the oxidization of the diffusion barrier layer pattern. A second interlayer dielectric pattern having a second contact hole exposing the surface of the first conductive film pattern is formed on the first interlayer dielectric film pattern and the first conductive film pattern. A second conductive film pattern used as the lower electrode of a capacitor is buried in the second contact hole and connected to the first conductive film pattern.