Abstract: A test logic circuit structure for performing a measurement operation on a semiconductor memory circuit device without requiring a negative supply voltage is provided which includes a comparator (38), a first resistive network (37) operatively connected to a first input of the comparator, and a second resistive network (35) operatively connected to a second input of the comparator. Verify logic circuitry (40) is used to switch the ratio of the value of the first resistive network to the value of the second resistive network defining a sense ratio to be less than one during a floor test mode so as to permit measurement of the threshold voltage of a programming array transistor (Q.sub.P) which is less than the threshold voltage of a reference cell transistor (Q.sub.R).

Abstract: A solid state switch is provided which has the capability of retaining its last state memory in the event of a power failure or interruption. The solid state switch includes an output driver formed of at least one N-channel MOS field-effect transistor, a holding capacitor, a charging resistor, a transistor-connected diode interconnected between a power supply voltage source and the charging resistor for preventing leakage of the holding capacitor. The field-effect transistor has its drain connected to a first output terminal and it source connected to a second output terminal. One end of the holding capacitor is connected to the gate of the field-effect transistor and its other end is connected to a ground potential. The holding capacitor retains the last state between the first and second output terminals in the event of a loss of the power supply voltage source.

Abstract: A high-speed CMOS-to-ECL translator circuit for receiving CMOS complementary input signals and for converting the CMOS input signals to ECL differential output signals includes a differential pair of MOS input transistors (N4,N3), a constant current source (I.sub.s), a first output stage, and a second output stage. The first output stage is formed of a first MOS output transistor (N2) and a second MOS output transistor (P1). The second output stage is formed of a third MOS output transistor (N2) and a fourth MOS output transistor (P2). The gates of the first and second input transistors (N4, N3) are responsive to the CMOS complementary input signals (D, DB). The first output stage generates one of the ECL differential output signals (Q) at a first output terminal (18), and the second output stage generates the other one of the ECL differential output signals (QB) at a second output terminal (20).

Abstract: A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels includes an output stage (20), first output buffer (22), a second output buffer (24), a first inptu circuit (26), and a second input circuit (28). The output stage (20) generates first and second output signals (Q1, Q2) at the respective first and second output noes (16, 18). The first output buffer is responsive to the first output signal (Q1) for generating a first buffered input signal (U1) which is CMOS logic compatible. The second output buffer (24) is responsive to the second output signal (Q2) for generating second buffered output signal (U2) which is CMOS logic compatible.

Abstract: A low voltage current mirror termination circuit used with an ECL gate array for providing a constant output emitter follower reference current (Ief) which is independent of voltage variations in a separate output emitter follower power supply source (VEF) includes a lateral PNP transistor (Qp), an NPN mirror transistor (Qx), at least one pull-down transistor (Qf), and at least one NPN output emitter follower transistor (Qo). The current through the collector of the lateral PNP transistor (Qp) defines a mirror current (Ip). The base of the lateral transistor (Qp) is connected to receive a base bias voltage VEP. The current through the collector of the pull-down transistor (Qf) defines the constant output emitter follower reference current (Ief) which is proportional to the mirror current (Ip). The separate emitter follower power supply source (VEF) has a voltage which is lower than a supply source (VEE) so as to reduce significantly the power consumption.

Abstract: A CMOS output buffer circuit for providing an output signal at an output terminal which has a significant reduction in ground bounce over processing and power supply variations includes an output driver stage (12), a pull-up pre-driver circuit (14), a pull-down pre-diver circuit (16), and feedback means. The output driver stage is formed of a pull-up transistor (P1) and a pull-down transistor (N1). The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby significantly reducing the ground bounce. The feedback means is preferably formed of a capacitor (C2) having a first plate connected to the output terminal and a second plate coupled to the gate electrode of the pull-down transistor.

Abstract: Glitch remover circuit for removing glitches and spikes from control signals received on a SCSI bus line that is coupled from a transmission line includes an input buffer circuit (12) and a filter circuit (14). The input buffer circuit is of a Schmitt trigger type having a transfer characteristic with hysteresis. The input buffer circuit (12) is responsive to control signals received at its input for removing noise spikes around the threshold point of its input on both the rising and falling edges of the control signals so as to provide a pulsed output voltage. The filter circuit (14) is responsive to the pulsed output voltage for generating a filtered pulsed signal at an output terminal only when the pulsed output voltage has a pulse width which is longer than a predetermined time. The filter circuit includes a delay means (28), a gating means (30) and inverter means (32).

Abstract: A lead cut and tape attach apparatus (10) for automatically cutting leads on one side of a semiconductor I.C. quad device and subsequently cutting and attaching a piece of tape over the gaps formed between the cut leads and for sequentially cutting the leads and attaching tape thereover on the remaining sides of the quad device includes a double-acting punch assembly (34) formed of an inner punch blade (58) and an outer punch (56). There is provided upper and lower cams (68, 78) for actuating the inner punch blade relative to the outer punch so that on a first downward stroke the inner punch blade is extended to cut the leads of the quad device. On a second downward stroke of the punch assembly, the inner punch blade is retracted and the outer punch cuts and attaches the tape.

Abstract: A tape dispenser for taping 90.degree. box corners includes a housing (12-20) for supporting a roll of tape to be dispensed therein, a first guiding member (30) for aligning the tape from the roll along the 90.degree. box corner to dispense a predetermined length of tape from the roll, a second guiding member (32, 34) for guiding initially the tape onto each side surface of the box forming the 90.degree. corner, and a third guiding member (42) for subsequently applying the tape onto the side surfaces of the box. A pair of blade carrying brackets (52, 54) is mounted for reciprocating vertical movement relative to the housing. A holder (58) is provided for receiving the blade carrying brackets for the reciprocating vertical movement therein. A cutting blade (56) is mounted to the lower ends of the blade carrying brackets. A cam actuating mechanism (76) is used to drive the blade carrying brackets downwardly to cause the blade to cut the tape which has been dispensed to the predetermined length.

Abstract: A pulse generator for generating an output pulse which is synchronized to an internal clock pulse includes a detector latch circuit (24), a master latch (12), a clocked latch (14), a first clocked half-latch (16), and an output logic circuit (18). Th detector latch (24) is responsive only to the positive edge of the asynchronous pulse of a varying width for generating a trigger signal which is latched to a low logic level. The master latch (12) is responsive to the trigger signal for generating a first latched signal which is latched to a high logic level. The clocked latch means (14) is responsive to the first latched signal and a first internal clock pulse signal for generating a second latched signal which is latched to a high logic level. The first clocked half-latch (16) is responsive to the second latched signal and a second internal clock pulse signal for generating a control signal.

Abstract: A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power disipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.

Abstract: An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current.

Abstract: A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin with a significant reduction in inductive ringing includes an output stage, a first delay network (38), and a second delay network (42). The output stage includes a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin. The common connection of the pull-up and pull-down transistors (P1, N1) are coupled to an output terminal pin. The first delay network (38) is interconnected between the first power supply terminal pin and a control electrode of the pull-up transistor (P1) for turning off the pull-up transistor (N1) so as to slow down the rate of rise of the output signal for a portion of the time when the output terminal pin is making a low-to-high transition so as to reduce the overshoot.

Abstract: A CMOS clock generator for generating internal CMOS phase clock signals having an adjustable overlap voltage includes a first circuit (18) having a first input responsive to an input clock signal for generating a first phase clock signal (01) on its output and a second circuit (22) having a first input responsive to the input clock signal for generating a second clock signal (02) on its output. The overlap voltage between the phase clock signals are adjustable either up or down to speed up or slow down a semiconductor chip after fabrication. This is achieved by the utilization of a laser to break or open up fuses connected to electrodes of transistor devices.

Abstract: A CMOS clamp circuit includes a sense inverter (I5) having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor (N5), and a P-channel MOS clamping transistor (P5). The N-channel clamping transistor (N5) has its drain connected to an upper power supply potential (VCC) and its source connected to the input node of the inverter (I5). The P-channel clamping transistor (P5) has its drain connected to a lower power supply potential (VSS) and its source connected to the input node of the sense inverter (I5). The gates of the N-channel and P-channel transistors (N5, P5) are connected to the output node of the sense inverter (I5). An enabling transistor and a power-down transistor may also be provided so as to operate the clamp circuit in a power-down mode of operation.

Abstract: A bipolar/CMOS ECL-to-CMOS conversion circuit for receiving ECL differential input signals and for converting the ECL input signals to CMOS complementary output signals, includes, a first output stage (20), a second output signal (22), a first base drive circuit (24), a second base drive circuit (26), a third base drive circuit (28), and a fourth base drive circuit (30). The first and second output stages are formed of bipolar transistors, and the first through fourth base drive circuits ar formed of CMOS transistors. The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the conversion circuit which has high current drive capabilities and low propagation delay regardless of variations in temperature and process corners.

Abstract: A TTL-to-CML translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals.

Abstract: A channel unit interface circuit for interconnecting a two-wire, bidirectional signal transmitting path and a four-wire signal transmitting path in a communication system includes a tip terminal transconductance amplifier driver, a ring terminal transconductance amplifier driver, a voice sense amplifier, a balance network, A/D signal processing circuit, D/A signal processing circuit, filter network, a voice codec/PCM filter, a channel logic circuit, and a DC-to-DC converter. The tip terminal transconductance driver is formed of a first switching operational amplifier, and the ring terminal transconductance driver is formed of a second switching operational amplifier. Each of the first and second switching operational amplifiers is formed of a low voltage transconductance amplifier, high voltage comparator, a filter network, and a feed forward compensation amplifier.

Abstract: A biasing circuit for use with memory cells in intermittent memories includes means coupled between first and second bit-lines for biasing continuously the first and second bit-lines during a read operation so as to compensate for any leakage of charge without consumption any power. The biasing means is formed of an N-channel MOS biasing transistor (M1) and a cross-coupled half-latch circuit formed of a first P-channel MOS transistor (M2) and a second P-channel MOS transistor (M3).

Abstract: An enhanced amplifier for interconnecting a two-wire, bidirectional cable side transmission path and a two-wire bidirectional equipment side transmission path in a communication system includes a first hybrid splitter and a second hybrid splitter. The first hybrid splitter is formed of a cable-to-equipment voltage sense amplifier, a shunt current driver, and a series current compensator for generating a first simulated terminating impedance. The second splitter is formed of an equipment-to-cable voltage sense amplifier, the shunt current driver and the series current compensator for generating a second simulated terminating impedance. Other features disclosed include automatic gain adjustment circuitry for automatically setting the gain in gain/equalizer circuits to a fixed level. Further, auto-balancing circuitry is provided for adjusting automatically and continuously both equipment and cable side balance networks.