Abstract: A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

Abstract: A .mu.BGA carrier for packing and shipping of a plurality of .mu.BGA packages is specially adapted for facilitating the inspection of the solder balls on the bottom surfaces of the .mu.BGA packages. The carrier consists of a tray member having a plurality of first pockets disposed therein for packing and storing the plurality of .mu.BGA packages, and a lid member having a plurality of second pockets formed therein. The second pockets are vertically aligned with corresponding ones of the plurality of first pockets in the tray member when the lid member is placed on top of the tray member. The carrier can be flipped upside-down so that when the tray member is removed the solder balls are facing upwardly to allow inspection of the same.

Abstract: A handler attachment device used for loading and unloading of wafer cassettes into and out of a spray processing tool is comprised of a rectangularly-shaped main body member, two U-shaped gripping members, and two L-shaped bracket members all interconnected together. The main body member includes a narrow middle section and opposed first and second end sections having angled mounting areas disposed therein. The two U-shaped gripping members are mounted to the corresponding first and second mounting areas on the body member. The two L-shaped bracket members are mounted to opposed side edges of the body member for engaging with the wafer cassette. The U-shaped gripping members are grasped by the corresponding hands of an operator in a manner so as to reduce and minimize fatigue and stress to his hands, wrists and arms.

Abstract: There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.

Abstract: There is provided a novel method for performing low current channel hot-carrier programming in a NAND memory architecture. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the select gate drain devices in the selected columns of bit lines during the programming operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the select gate drain device and to the word lines of unselected memory cells so as to overlap the first positive pulse voltage. Further, a ramp voltage is applied to the word line of selected memory cells so as to permit fast programming thereof.

Abstract: A CMOS transmission line equalizer is provided for receiving distorted signals transmitted through a transmission line and for compensating for the signal distortion. The equalizer has a transfer function characteristic with a single pole and a single zero. The transfer function includes a mirroring ratio circuit (CMR) for controlling the ratio between the single pole and the single zero. The mirroring ratio circuit is controlled by transistor size ratio. The single zero serves to cancel the dominant pole in the transfer function of the transmission line so as to compensate for the signal distortion caused by the transmission line.

Abstract: A programmable logic device operable to generate different control signals during a time interval when it is being reconfigured includes a plurality of I/O pins (18a-18f), boundary scan circuitry (14) operatively connected to the I/O pins for loading a new set of data and for driving the new set of data onto the I/O pins, and means for programming (33) the programmable logic device on a row-by-row basis when loaded with program instructions. Control circuitry (31a) is provided to control the programming means to be operated on a self-timed interval for programming each row so that the boundary scan circuitry can be loaded with additional sets of data to generate the different control signals. The control circuitry includes a programming timer register (70) and a programming status register (68).

Abstract: A faulted indicator elbow-type termination connector for indicating the occurrence of a fault current in an electrical conductor of an alternating current distribution power system includes means for producing a magnetic field in response to an applied current to the electrical conductor. The termination connector includes a cylindrical body portion having a recessed housing section which projects radially from a central axis thereof. A faulted circuit indicator module is rotatably mounted within the recessed housing section and contains a trip setting device which is responsive to the magnetic field. The trip setting device has its sensitivity adjusted by rotating the faulted circuit indicator module relative to the cylindrical body portion. As a result, the sensitivity of the trip setting device can be changed quickly and easily so as to accommodate various trip settings.

Abstract: There is provided an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation. The array has a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting the rows of word lines. A programming current source is connected to the source of selected memory cells that are to be programmed in the corresponding columns of bit lines. A programming gate voltage is applied to control gates of the selected memory cells, and a programming drain voltage is applied simultaneously to the common array ground line connected to the drains of all of the memory cells. Further, a relatively low voltage is applied simultaneously to all of the control gates of non-selected memory cells in the array which are not to be programmed during the programming operation so as to eliminate the program disturb.

Abstract: A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.

Abstract: The present invention provides a method of producing in a single in-line process a printed image suitable for creating an illusion of depth in the perception of a viewer of the image, comprising the steps of:(1) providing an opaque web to an in-line printing process,(2) providing a transparent web to the in-line printing process, the transparent web having a lenticular surface on one side and a flat surface on an opposing side,(3) transporting either the opaque web or the transparent web to a first printer unit of the in-line printing process at a preselected speed and printing a line-formed image on the opaque web or the flat surface of the transparent web, the line-formed image being compatible for viewing when viewed through the lenticular surface of the transparent web, and(4) setting the image on either the opaque web or flat surface of the transparent web in a heat setting unit of the in-line printing process.

Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.

Abstract: A faulted circuit indicator includes a variable load levelling circuit which can automatically adjust itself to a peak current in order to accommodate a relatively wide range of load currents. The variable load levelling circuit is operatively connected to a current sensing circuit and is responsive to a varying load current flowing through the cable for regulating a variable output voltage therefrom to be at a constant reference value. As a result, the need to store in inventory large quantities of fault indicators with different rated currents has been substantially reduced.

Abstract: A faulted circuit indicator unit for detecting an abnormally high electric current in an overhead cable includes a substantially rectangularly-shaped housing formed of front and back walls, opposed side walls, a closed bottom wall, and an open top mouth portion. Current sensing circuitry is disposed in a cavity formed in the housing for detecting the high current in the cable. An indication device is joined to the closed bottom wall of the housing and includes a visible indicator responsive to the current sensing circuit to produce a visual flashing light in the presence of the high current which is visible through a small aperture formed in the bottom wall thereof. The indication device is formed of an opaque hood whose central portion is connected around the bottom wall of the housing and a transparent stem joined also to the central portion of the hood and extends downwardly therefrom through which the flashing light is transmitted radially outwardly in all directions.

Abstract: An improved EEPROM structure is provided which has a longer data retention period. This is achieved by utilizing only positive charges to store data on the floating gate. The EEPROM structure includes a write select transistor (112), a read select transistor (120), and a floating gate sense transistor (126). The source of the write select transistor is capacitively coupled to the floating gate of the floating gate sense transistor via a tunnel oxide layer (145). The floating gate of the floating gate sense transistor is also capacitively coupled to a control gate line (CG) via a gate oxide layer (153). The sense transistor is formed as an enhancement transistor so as to allow the EEPROM structure to be operated in a region where the floating gate potential is positive for both programmed and erased conditions, thereby using only the positive charges to store data.

Abstract: A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.

Abstract: A web tensioning device to maintain a pre-selected web tension during web delivery and web roller take-up. The device comprises a web pressure sensing roller, tension pre-selection and conditioning circuitry means associated therewith. A motor controller responsive to condition circuitry input selectively controlling a supply roller.

Abstract: A self-calibrating temperature controller adapted for use in controlling closely the temperature of hot-melt adhesive dispensed from an adhesive supply unit is provided. The temperature controller includes a microcomputer operated under a stored program to perform automatically a self-calibrating operation. A non-volatile memory is provided for storing RTD values in a lookup table so as to compensate for the non-linearity of the RTD sensors.

Abstract: An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selected together with a selected memory core cell. A precharge circuit (36a) is used to precharge all of the array bit lines and the reference bit lines to a predetermined potential prior to a program operation. A reference generator circuit (134) is used for selectively generating one of a plurality of target memory core cell bit line program-verify voltages, each one corresponding to one of a plurality of programmable memory states. A switching circuit (P1,N1) is used to selectively connect a program current source to the selected certain ones of the columns of array bit lines containing the selected memory core cells which are to be programmed.

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.