Abstract: An exemplary description provided for patent searches includes a linear electrodynamic system involving conversions between electrical power and mechanical motion uses unique magnet assemblies that move and unique stator assemblies and stator members shaped and oriented with respect to the moving magnet assemblies.

Abstract: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

Abstract: For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a wordline can store are written concurrently. More than one, but less than all of the logical pages that a physical page along a wordline can store are then written concurrently on an adjacent wordline. The process then comes back to the first wordline and writes at least one more logical page. A process is also described where one or more logical pages are written into a physical page along a wordline, after which one or more logical pages are written into a physical page along an adjacent wordline. A read operation is then performed on the first wordline and the resultant read is corrected based on the result of programming the adjacent wordline. This corrected read is then used in writing at least one more logical page in a second programming operation on the first wordline.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A method of operating a communication system is disclosed. The method includes transmitting from a remote unit to a base station remote unit channel data. The remote unit channel is generated at the remote unit and includes data about a first portion of communication channels on which the call can be executed. The method also includes applying a channel selection method to the remote unit channel data and to base station channel data so as to select a communication channel from among the first portion of communication channels. The base station channel data is generated at the base station and includes data about a second portion of the communication channels. The method further includes executing a call on the selected communication channel.

Abstract: There is provided an apparatus 2 for generating electrical charge from a motive power source 3. The apparatus 2 comprises an alternator 3a and a worm drive assembly 4 connectable to the motive power source 3. The worm drive assembly 4 comprises a drive shaft 14 a worm gear 20; and, a worm wheel 32 configured so as to mesh with the worm gear 20 and as is further arranged so as to be operatively associated with the alternator 3a. During use, rotation of the drive shaft 14 by the motive power source 3 effects generation of electrical charge by the alternator 3a.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.

Abstract: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

Abstract: The invention relates to a music notation system that obviates the need for one to have any knowledge of conventional music notation in order to play a keyboard, including those that are a component of a conventional musical instrument, those that are a component of an electronic musical instrument and those that are configured as a user interface with a computer system and/or video game.

Abstract: Pixel intensities indicative of scattered radiation from portions of the inspected surface surrounding a location of a potential anomaly are also stored so that such data is available for quick review of the pixel intensities within a patch on the surface containing the location of the potential anomaly. Where rotational motion is caused between the illumination beam and the inspected surface, signal-to-noise ratio may be improved by comparing the pixel intensities of pixels at corresponding positions on two different surfaces that are inspected, where corresponding pixels at the same relative locations on the two different surfaces are illuminated and scattered radiation therefrom collected and detected under the same optical conditions.

Abstract: A method for extending the useful life of an in-service electrical cable section having a stranded conductor surrounded by a conductor shield encased in a polymeric insulation jacket and having an interstitial void volume in the region of the conductor, the cable section having an average conductor temperature T. The method comprising (i) continuously introducing a non-condensing exclusion fluid into the interstitial volume, the exclusion fluid comprising at least one non-condensing exclusion component having a solubility in the insulation polymer at least 100 times the corresponding solubility of water, each solubility being determined at temperature T; and (ii) injecting a condensing dielectric enhancement fluid into the interstitial void volume, wherein the dielectric enhancement fluid has a virtual flow rate within the interstitial void volume of less than about 0.1 liter per hour.

Abstract: A system and method are described for broadcasting/multicasting content using surplus network capacity. The systems and methods are directed to solving the problem of how to simultaneously broadcast/multicast large content files to a plurality of users for later retrieval by using existing network capacity as opposed to being forced to add new capacity to handle peak demand. Generally, the methods comprise receiving data to be distributed, determining surplus network capacity, and distributing the data within the surplus network capacity to a plurality of subscriber devices.

Abstract: Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines.

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract: A charge pump system using a current based regulation method, in addition to the typical voltage based regulation methods is presented. The current flow in the charge pump is determined independently of the output voltage. By sensing the current going through the charge pump while its output is being regulated to the target level, the strength of charge pump can be dynamically adjusted in term of regulation level, branch assignment, clock frequency, clock amplitude, and so on. Indirectly sensing the current going through pump (not in serial with output stage to allow additional IR drop) will allow the pumps to have matrix of V and I to better adjust the charge pump parameters for current saving and ripple reduction.

Abstract: A lighting system for illuminating a chamber in a building includes a lighting fixture suitable for being mounted onto a surface of the chamber, so that light emitted by at least one CCFL device mechanically supported by the fixture illuminates the chamber. The one CCFL device includes at least one transformer. A driver adapted to be connected to a surface of the chamber is capable of converting input power from a power source to an AC power having a voltage in the range of about 5-400 volts and a current at a frequency in the range of about 1kc-100 kc. The at least one transformer is suitable for converting the AC power to an output power suitable for operating the at least one CCFL, causing the at least one CCFL to emit light.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

Abstract: A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series and a corresponding set of multiple gate stages connected in series, where the output stages have the same structure as the corresponding gate stages. The switches that the provide the output of each output generation stage are controlled by the corresponding gate stage. The number of output stages that are active in boosting the voltage self-adapts according to the output level being regulated, with the later stages changing from a boosting operation to a filtering function with not being used to active boost the output.