Abstract: The invention disclosed herein is directed to methods of identifying a polypeptide suitable for epitope liberation including, for example, the steps of identifying an epitope of interest; providing a substrate polypeptide sequence including the epitope, wherein the substrate polypeptide permits processing by a proteasome; contacting the substrate polypeptide with a composition including the proteasome, under conditions that support processing of the substrate polypeptide by the proteasome; and assaying for liberation of the epitope. The invention further relates to vectors including a housekeeping epitope expression cassette. The invention relates to epitope cluster regions and to vectors including epitope cluster regions. The invention also relates to a method of activating a T cell comprising contacting a substrate polypeptide with an APC and contacting the APC with a T cell.

Abstract: Disclosed herein is an initiator integrated polydimethylsiloxane (iPDMS). The iPDMS is a polydimethylsiloxane undergoing a hydrosilylation reaction. The initiator 10-undecenyl 2-bromo-2-methyl propionate is integrated on the surface of iPDMS by covalent bond. At % is 0.01-1% confirmed by X-ray photoelectron spectroscopy. Disclosed herein is a method for making an initiator integrated polydimethylsiloxane. Prepolymer A, cross-linker B and vinyl-terminated initiator C were mixed below a ratio of 10:1:4-0.01 for 6-24 hours, then the elastomer was formed. And, disclosed herein is functional surface modification of initiator integrated polydimethylsiloxane and its applications for biocompatibility, organic solvent compatibility and heat-sensitive materials.

Abstract: A system for destroying a memory device (e.g., a hard drive) having data stored thereon. The system has a grind chamber with a rotatable grind wheel positioned therein. A pressure arm presses the memory device against the grind wheel as the grind wheel rotates. The rotating grind wheel grinds the memory device into particles from which the data stored on the memory device cannot be recovered. The particles are collected in a receptacle adjacent the grind wheel. The system may include a plurality of guides configured to maintain the memory device in a substantially stationary position relative to the pressure arm as the grind wheel grinds the memory device into particles.

Abstract: The present invention describes an apparatus, a system and a method for the treatment of obstructive sleep apnea. The treatment involves monitoring the position of the tongue and/or the force exerted by the tongue and electrical stimulation of the hypoglossal nerve to move the tongue into an anterior position or to maintain the tongue in an anterior position.

Abstract: A chute for inspection and sorting apparatus has first and second flat sections, with the lower end of the first section being disposed over the second section to form a step from which product falls onto the second section. Additional sections may be included. In one variant a third channeled section is included, with the lower end of the second section being disposed over the third section forming a second step from which product falls onto the third section.

Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.

Abstract: A telephony application such as an interactive voice response (“IVR”) needs to identify quickly the nature of the call (e.g., whether it is a person or machine answering a call) in order to initiate an appropriate voice application. Conventionally, the call stream is sent to a call-progress analyzer (“CPA”) for analysis. Once a result is reached, the call stream is redirected to a call processing unit running the IVR according to the analyzed result. The present scheme feeds the call stream simultaneous to both the CPA and the IVR. The CPA is allowed to continue analyzing and outputting a series of analysis results until a predetermined result appears. In the meantime, the IVR can dynamically adapt itself to the latest analysis results and interact with the call with a minimum of delay.

Abstract: Methods, systems and computer-readable code for maintaining flash data structures in accordance with events of a flash memory system are disclosed. Both an events log as well as at least one flash management table are maintained in flash memory. For at least one point in time, a most recently stored flash memory table is indicative of an earlier state of the flash memory system, while at least one event that is more recent than the earlier state is stored in the events log. During power-up, the flash management table is retrieved from flash memory. If the most recent event of the flash memory table is earlier than the most recent event of the events log, events are retrieved from the events log in order to update the flash memory table. Optionally, the updated flash memory table is saved to flash memory.

Abstract: Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M?1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Abstract: A substrate operable to construct a male-type connector, a female-type connector, and/or a multi-outlet module. The substrate has a plurality of circuits and an edge card male connector including contacts for each circuit. For each circuit, the substrate has a ground plane connected to one or more of the contacts for the circuit. The ground planes may be implemented as localized, electrically floating, isolated ground planes. The substrate may include multiple layers upon which portions of the circuits and ground planes may be disposed. The ground plane corresponding to each of the plurality of circuits may be located in close proximity to conductive elements of the circuit so as to provide a localized common ground to which energy can be conveyed from the conductive elements to thereby limit an amount of energy radiated outwardly from the conductive elements to surrounding conductors.

Abstract: In a nonvolatile memory with block management system, critical data such as control data for the block management system is maintained in duplicates. Various methods are described for robustly writing and reading two copies of critical data in multi-state memory. In another aspect of the invention, a preemptive garbage collection on memory block containing control data avoids an undesirable situation where a large number of such memory blocks need be garbage collected at the same time.

Abstract: The present invention is related to methods and compositions that are capable of immediately immunizing a human or animal against any molecule or compound. The present invention comprises an immunity linker molecule with at least two sites; (1) a first binding site that binds to an immune system molecule in a human or animal that has been preimmunized against the first binding site, and (2) one or more second binding sites that bind specifically to a desired compound or molecule. The first binding site and the second binding site(s) are linked by a linker portion of the molecule.

Abstract: A supplement dispensing closure couplable to an outlet of a container, such as a water container. When the closure is coupled to the container, liquid exiting the container through the outlet flows through a supplement retention area that retains a dissolvable supplement body inside the closure as the liquid flows therethrough and dissolves the dissolvable supplement body. A user may select one or more dissolvable supplement bodies and insert them inside the supplement retention area for dissolution in the liquid as it flows through the supplement retention area. The closure may include a selectively openable and closable cap portion. Optionally, the closure includes a filter configured to filter one or more components from the liquid before or after it flows through the supplement retention area.

Abstract: The present invention concerns a method for the manufacture of a 5-substituted 2-(alkoxymethyl)furan (or a mixture of such furans) by reacting a starting material comprising at least a 5-substituted furfural with hydrogen in the presence of an alcohol and a catalyst system.

Abstract: A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

Abstract: A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

Abstract: The present invention provides novel viscous and adherent food-safe antimicrobial compositions, and methods for using same in the immediate and residual decontamination of microbial-contaminated substrate surfaces, in reducing or precluding cutting implement-mediated transfer of surface contamination during cutting operations in the food industry, and for reducing or preventing transfer of contamination from contaminated surfaces in the food and pharmaceutical. Adherent antimicrobial protective layers are formed on substrate surfaces (e.g., processing equipment and utensils), providing a barrier (e.g., chemical and/or physical) to the passage or transport of microbial contamination between and among surfaces. The adherent formulations confer residual de-contaminating activity, providing for prolonged killing of associated microbial contamination.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.