Abstract: A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned recording media. The preamplifier contains a write pre-driver that conditions write data, a synchronization circuit that accepts a delay offset value and a write clock and produces a delayed clock, and a write output driver that is gated by the delayed clock to produce write pulses for magnetizing the bit islands. Gating the write output driver using the delayed clock results in more accurate synchronization than delaying the write data into the preamplifier due to the reduction of the overall length and variability of interconnects and transistors in the intervening circuitry.

Abstract: A current gain control system is described and comprises first and second gain blocks respectively associated with the first and second input channels, wherein first and second gain blocks transmit first and second gain signals in response to receiving first and second input signals; first and second converters adapted to be respectively coupled to the first and second gain blocks, the first and second converters operative for setting gains associated with the first and second input channel and for transmitting first and second converted signals in response to receiving the first and second gain signals; and first and second switches for selectively coupling the first and second converters to first and second channel drivers, respectively, wherein the first and second channel drivers transmit channel gain signals in response to receiving the first converted signal, and the channel gain signal allows control of the gain associated with the input channel.

Abstract: Systems and methods are provided for determining mechanical resonance of a sensor. In one embodiment, a system is provided that comprises a bias voltage source configured to apply a bias voltage impulse signal to a terminal of the sensor and a zero crossing detector configured to detect zero crossing cycles of a sensor output signal response to the bias voltage impulse signal. The system further comprises a controller configured to determine the resonance frequency of the sensor based on the detected zero crossing cycles of the sensor output signal response.

Abstract: A disk drive data storage system. The system comprises a data storage disk, a movable member positioned near the data storage disk, and a sensor assembly, supported and movable by the movable member, for writing data to and reading data from the data storage disk. The system also comprises an integrated circuit that is electrically coupled to the sensor assembly and that moves with the movable member when the movable member moves the sensor assembly. The integrated circuit comprises a face and a backside, and the integrated circuit is in a fixed physical position relative to the movable member such that the backside is oriented toward the movable member.

Abstract: Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes testing the SoC using the at least one input scan chain and the at least one output scan chain of each core.

Abstract: Methods and apparatus for generating a hard drive write signal are here in disclosed. A disclosed method comprises generating a hard drive write signal on an output of a switch based on an edge of the first control signal and reducing the hard drive write signal based on an edge of a second control signal via a second switch.

Abstract: The present invention relates to pre-distortion in transmitter circuits and provides a circuit for introducing pre-distortion into the output of a transmitter, wherein said pre-distortion comprises a pre-cursor, a cursor and a post-cursor, the circuit comprising: a first driver arranged to switch an output drive between said pre-cursor and said cursor; a second driver arranged to switch an output drive between said post-cursor and said cursor; a third driver arranged to switch an output drive between a positive cursor drive and a negative cursor drive. The arrangement provided give flexibility when setting the pre-cursor, cursor and post-cursor levels.

Abstract: Methods and apparatus to reduce the stopping time of a spindle motor are disclosed. An example method includes detecting a dissipation current flowing in a spinning motor; determining when the dissipation current drops below a threshold value; and, in response to the dissipation current dropping below the threshold value, applying a voltage to the motor to increase the dissipation current for a duration. In some examples, the voltage is removed from the motor when the motor reaches a predetermined rotational velocity to avoid reverse rotation.

Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) system. A resistive ladder comprises a plurality of resistors having an approximately equal resistance and is arranged in a respective plurality of resistive rungs between first and second ends of the resistive ladder. The first end of the resistive ladder can be coupled to an output and at least a portion of the plurality of resistors between the first end and the second end of the resistive ladder can have a physical size that is descending size-scaled in a direction from the first end of the resistive ladder to the second end of the resistive ladder. A switching circuit is configured to connect each of the plurality of resistive rungs to one of a first voltage and a second voltage based on a binary value of a digital input signal to generate a corresponding analog output voltage at the output.

Abstract: A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have a first parallel data width. At least one of the syndromes is produced based on a corresponding at least one of the sets that has a second parallel data width that is less than the first parallel data width. The last syndrome of the sequence of syndromes corresponds to all of the data in the received sequence of sets.

Abstract: A circuit for providing a write current having a programmably adjustable duty cycle in a hard disk drive write channel has a differential pair gain circuit for receiving a data input signal and generating a differential output voltage to provide a differential write signal for generating the write current. First and second programmable current sources are connected to the differential pair gain circuit to create a programmable voltage offset of the differential output voltage to programmably adjust the duty cycle of the write current.

Abstract: An over current protection device is described. It includes a plurality of input channels for receiving an input signal; a plurality of low pass filters coupled to a first group of the plurality of input channels, wherein each low pass filter is associated with one input channel within the first group of input channels, the plurality of low pass filters operative for removing spikes in associated with the input signal; and a plurality of digital to analog converters coupled to a second group of the plurality of input channels, wherein each digital to analog converter is associated with one low pass filter in the second group of input channels, the digital to analog converters operative for triggering over current protection when a signal received from the associated low pass filter is beyond a preset level, wherein the over current protection device is on chip with the laser diode driver.

Abstract: A modulation control system for use with a high frequency modulator is described. This system comprises a latch for selectively receiving enable signals, wherein the latch transmits a latched signal in response to receiving at least two of the enable signals; a selection device coupled to the latch for receiving the latched signal, a voltage source, and a terminal for receiving at least one of the enable signals, wherein the selection device transmits a selected signal; and a logic device coupled to the selection device and a terminal for receiving a modulated enable signal, wherein the logic device transmits a synchronized signal for either enabling or disabling the high frequency modulator in response to receiving the selected signal associated with at least one of the enable signals.

Abstract: A reverse current sensing (RCS) regulator system and method is provided. One embodiment of the invention includes a RCS regulator system. The system comprises a RCS comparator that monitors a drain voltage of a LS FET and is configured to switch states at a zero crossing point to provide an indication of the start of a reverse current condition. The system further comprises a RCS evaluator that measures a drain voltage of the LS FET upon receiving an indication that the LS FET has been turned off by the driver logic circuit and adjusts an offset to the RCS comparator to adjust the trip point of the RCS comparator relative to the drain voltage if the measured drain voltage falls outside a predetermined threshold.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: Methods and apparatus to lock a phase lock loop to a spindle motor are disclosed. An example controller comprises a counter to determine a period of an operating signal received from a motor, an oscillator to generate a control signal based on an input signal, and an initializer to generate the input value based on the period, wherein the input value causes the oscillator to generate the control signal having the same phase as the operating signal.

Abstract: Resistivity sense bias circuits are described herein. An example resistivity sense bias circuit for use with a magnetoresistive read head includes a current biasing portion configured to provide a bias current across the magnetoresistive read head thereby establishing a bias voltage across the magnetoresistive read head, a resistivity sensing portion coupled to the current biasing portion and configured to sense a change in the bias current based on a resistivity change of the magnetoresistive read head, and a voltage source to provide the bias voltage and to adjust the bias voltage in response to the resistivity change of the magnetoresistive read head.

Abstract: One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a first current path that includes a first degeneration resistance device and to generate an output current that flows through a second current path that includes a second degeneration resistance device. The output current can be substantially proportional to the input current. The system also includes a degeneration control circuit configured to maintain a substantially constant degeneration voltage across each of the first and second degeneration resistance devices.

Abstract: A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions.