Abstract: Methods and apparatus to monitor and control hard-disk drive head position are described. In one example, a hard-disk drive system includes a hard-disk drive platter, a hard-disk drive read head configured to read information from the hard-disk drive platter, and a hard-disk drive head position controller configured to a receive a signal via the hard-disk drive read head and to determine if the received signal indicates that a distance between the hard-disk drive platter and the hard-disk drive is less than a predetermined distance and to vary a temperature of the read head based on the determination.

Abstract: An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a combinational logic circuit that performs a logical operation on a second input signal and a clock signal. The output of the transmission circuit is coupled to a digital storage element. Further, a control circuit is coupled to the digital storage element in order to force a value on the digital storage element when no input signal is received from the transmission circuit. The control circuit is also controlled by the second input signal and a clock signal.

Abstract: The image sensing system includes integrating charge in an image sensor array; transferring the charge out of the image sensor array; converting the charge to a digital signal; combining the digital signal with digital data stored in a memory device to form an integrated signal; storing the integrated signal in the memory device such that the integrated signal becomes the digital data; and repeating the above steps multiple times during a frame time cycle. This system allows for very small pixel sizes in the image sensor. The digital integration process eliminates the need for using correlated double sampling circuits to reduce kTC noise, and is also beneficial for reduction of analog-to-digital digitization noise.

Abstract: In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module including a first sub-level module, a second sub-level module operably coupleable to the first sub-level module, and a third sub-level module operably coupleable to the second module; and a second-level module operably coupleable to the first-level module is disclosed.

Abstract: One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system includes a current distributor configured to generate a reference current and to decay the reference current from a first magnitude to a second magnitude during a degauss period to degauss a magnetic disk write head. The degauss period defines a transition from a write cycle to a read cycle of the magnetic disk-drive and has a predetermined time duration that is independent of the first magnitude of the reference current during the write cycle. An output driver is configured to provide a write current to the magnetic disk write head having a magnitude with an absolute value that is based on the reference current.

Abstract: A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element.

Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

Abstract: A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal.

Abstract: A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.

Abstract: A square-function circuit includes an input field-effect transistor (FET) having a gate that is driven by an input voltage and is configured to conduct an output current. The circuit also includes a feedback circuit coupled to a source of the input FET, the feedback circuit being configured to drive a source of the input FET based on the output current to set a magnitude of the output current to be substantially equal to a square of the input voltage.

Abstract: An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a second pMOS gate terminal of a second pMOS transistor of the pair of pMOS transistors, and tying at least a first pre-designated body terminal of at least one transistor selected from the group including essentially of a pair of pMOS transistors and a pair of nMOS transistors to at least a second pre-designated terminal of at least one pre-designated transistor selected from the group including essentially of the pair of pMOS transistors and the pair of nMOS transistors.

Abstract: A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.

Abstract: Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncompliance are adapted to bring the layout within the design rules. In a preferred embodiment of the invention monitoring the relative positions of macros includes identifying instances of coinciding macro (x, y) coordinates. Adapting noncompliant macros further includes steps for maintaining minimum (x, y) distances between adjacent macro corners.

Abstract: In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer.

Abstract: A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one embodiment, a method of timing the precharging of BLs in a self timed compiler memory array includes initiating an internal clock during the start of a read/write cycle by a control block, triggering DWL and WLs to go high upon initiating the internal clock by the control block, triggering DBL and BLs to go low upon the DWL and WLs going high by the control block, generating a reset BL signal upon the DWL going high and the DBL going low by the tracking circuit, disabling the DBL from going further low upon receiving the reset BL signal by the tracking circuit, and precharging the DBL to go high upon receiving the reset BL signal by the precharge circuit.

Abstract: A novel schematic for executing search, write and valid bit clear operations in one cycle in a CAM system that includes a plurality of CAM blocks is disclosed. In one embodiment, the plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. The write operation depends on the output of the search operation, wherein the same data is written in to the CAM when the search operation results in a miss in a given cycle. Further, during the same cycle a valid bit clear operation is also performed. The resulting CAM cell provides a high speed three port operation.

Abstract: A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

Abstract: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9?? a through any metal segment in the parametrically modeled circuit.

Abstract: Methods and apparatus to provide dynamically biased write drivers for hard disk drive applications are described. According to one example, a hard disk drive write system includes a drive signal generator to receive data to be written to a hard disk drive platter and to generate drive signals including a boost signal. A drive circuit is configured to receive the drive signals and to generate currents for output to the transmission line based thereon, wherein the currents include a boost current. A variable bias circuit is configured to detect the boost signal generated by the drive signal generator and to vary a bias signal provided to the impedance matching circuit based on the detection of the boost signal. In such an example arrangement, the impedance matching circuit matches impedances between the drive circuit and the transmission line in response to the bias signal provided by the variable bias circuit.

Abstract: An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.