Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two parallel-coupled stages having an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This adjustment circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: A device for automatically converting a digital sample sequence X(n) inputted at a first frequency fe and converted into an output digital sample sequence Y(m) at a second frequency fs which is smaller than fe. An interpolator-decimator assembly having a decimation rate equal to &ggr;, selected so as to correspond to the frequency offset fe/fs is based on a polyphased filter having p tables of q elements each, said filter being designed such that samples X(n) are input at the fe frequency and table components are activated according to clocking of a second clock derived from the fe clock and wherein one clock pulse is removed.

Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract: A dynamic or non-volatile memory with a differential reading system with improved load rebalancing comprising a rebalancing circuit that for values of the supply and memory selection voltage in excess of a predetermined reference voltage modifies one or the other of two currents, i.e., the measuring current or the reference current, with an equivalent effect on the load rebalancing.

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: A variable gain amplifier is described which comprises a first device to which a first control signal (Vc, Vc1) is applied so that the gain (Ai1, Ai) of an output signal (iout, io) of the first device (11, 22, Q45-Q48) with respect to a first input signal (in, i1, ir) is a function of the exponential type of the first control signal (Vc, Vc1). The amplifier comprises a feedback network (25, Q51-Q58) connected between an output terminal and an input terminal of the first device (22, Q45-Q48) so as to assure that the gain (Ai) in decibel of the first device (22, Q45-Q48) is a linear function of the first control signal (Vc1).

Abstract: A method and apparatus for measuring pulmonary blood flow in a subject by pulmonary exchange of oxygen and an inert gas with the blood using a divided respiratory system. One method of isolating two or more divisions of the respiratory system uses a multi-lumen cuffed endobronchial catheter. In one embodiment, a triple-lumen cuffed endobronchial catheter is provided. In another embodiment, gas mixtures are supplied to each lumen using a bag-in-a-box type ventilator for each breathing system for synchronizing the rate and pressure of mixed gas supplied to the lumens.

Abstract: The converter uses the energy stored in the output filter of a step-down (or buck) converter and in the inductor of a step up/down (or buck-boost) converter to supply a second output of opposite sign. In particular, the converter has a first input receiving an input voltage; a first output supplying a first output voltage of a first sign; a second output supplying a second output voltage of opposite sign; a controlled switch connected between the first input and a first intermediate node; an inductor connected between the first intermediate node and the first output; a diode connected between the first intermediate node and a second intermediate node; and a dual voltage generating circuit connected between the second intermediate node and the second output.

Abstract: The present invention relates to a rod-shaped preform for manufacturing an optical fiber therefrom, as well as to a method for manufacturing such a rod-shaped preform. The present invention furthermore relates to a method for manufacturing an optical fiber, wherein one end of a rod-shaped preform is subjected to a heat treatment, after which the thus softened end of the rod-shaped preform is subjected to a pulling force for the purpose of drawing an optical fiber therefrom.

Abstract: An inductance arrangement is directed to inductors, chokes and transformers with a very high power density. Chokes comprise a magnetic circuit and an electrical circuit, the latter usually comprising a copper winding. The inductance arrangement improves cooling of the magnetic circuit, efficiency of the induction arrangement, and reduces the consumption of material for the windings for a lower weight and a reduced structural size. Individual plate packs in the induction arrangement are displaced relative to each other to increase the surface area at both sides of the iron core. Displacement of the plates of the limbs allows for effective cooling passages or ducts between the core and the surrounding winding.

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract: A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: A protective envelope, made of a plastics material for enclosing a semiconductor integrated circuit, includes a flattened parallelepiped body having a sidewall formed of first and second portions set to converge toward each other. The envelope also includes a lead frame embedded in the body and bearing the integrated circuit, the lead frame having a section bent to form a baffle plate orientated toward the first sidewall portion. Advantageously, the bent section of the lead frame has a plane end edge extending parallel to the first sidewall portion at a spacing therefrom.

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract: Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.

Abstract: The invention relates to a circuit generating a voltage signal which is independent of temperature and has low sensitivity to variations in process parameters, comprising at least an output MOS transistor through which an output current flows, it being connected to a first voltage reference and having a gate terminal connected to a bias network, in turn connected between a second voltage reference and the first voltage reference. The circuit of this invention includes a bias network comprising at least first and second MOS transistors connected in a diode configuration, connected in series between said first and second voltage references, and connected to the second voltage reference through a current generator element having a thermal gradient that approximates the thermal gradient of a MOS transistor.

Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

Abstract: Described is a method to form isolation structures on a semiconductor substrate. This method begins with forming one or more trenches in the semiconductor substrate and depositing a first portion of a dielectric layer at a first rate by a High Density Plasma—Chemical Vapor Deposition into the trenches and onto the semiconductor substrate. This first deposition at least partially fills the trenches and may completely fill the trenches. Next, a second portion of the dielectric layer is deposited at a second rate by the High Density Plasma—Chemical Vapor Deposition over the semiconductor substrate to partially planarize the dielectric layer. This second deposition is preferably performed with a different flow rate of reaction gasses than the first deposition. Finally, a portion of the dielectric layer that was deposited at the second rate is removed by a CMP process, for example.