Abstract: A final stage for a high-speed comparator, and a method of driving an electric load having a capacitive component are disclosed. The final stage comprises a first or pull-up component and a second or pull-down component which are connected in series with each other between a first or supply voltage reference and a second voltage reference. A dynamic drive device and a separate static drive device are coupled to each component of the output stage. Each component of the final stage is driven separately according to whether it is in a static or a dynamic load condition.

Abstract: A power modulation control system using PWM pulses is provided. The system comprises an AC voltage generator, an electric load, and a control circuit incorporating at least one rectifier. The electric load is connected between the generator and the rectifier, and first and second monodirectional switches are connected in parallel with the load.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: An amplifier stage for a buffer with negative feedback includes an input stage having an input terminal, an output terminal, a first and a second supply terminal, a biasing branch, a first and a second balancing branch each comprising an active transistor for supplying, at the output terminal, a current depending on the current difference in the first and second balancing branches. The biasing branch and the first and second balancing branches are connected in parallel between the first and second supply terminals. The input terminal divides the biasing branch into two input branches having a constant-current generator. Each active transistor is connected to a corresponding current generator for receiving a control voltage correlated with a voltage at the terminals of the current generator.

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract: The integrated electronic device comprises a protection structure of metal, extending vertically and laterally to and along a predominant part of the periphery of an electronic component integrated underneath the pad region. The protection structure comprises a substantially annular region formed from a second metal layer and absorbing the stresses exerted on the pad during wire bonding. The annular region may be floating or form part of the path connecting the pad to the electronic component.

Abstract: A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has first positive voltage generator means for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.

Abstract: The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads.