Abstract: A method and system are disclosed for managing access to system resources by a user process within a multitasking data processing system. The data processing system includes a processor for executing kernel threads scheduled to the processor and a memory having a user address space which stores an application program and a kernel address space which stores an operating system kernel. The operating system kernel includes a kernel process comprising one or more first kernel threads which can each access the system resources. The user address space also stores a user process which has ownership of the system resources. The user process includes a second kernel thread comprising instructions within the application program. To access certain system resources, the second kernel thread invokes a first kernel thread within the user process.

Abstract: A client process resides on a host computer within a distributed data processing system, and the client process requests a remote procedure call for a service procedure. A binding handle of a server process is obtained; a determination is made as to whether the binding handle of the server process points to the client process; and in response to a determination that the binding handle of the server process points to the client process, a positive indication is generated that the service procedure is provided by the client process. In response to a determination that the service procedure is provided by the client process, the service procedure is called using a local procedure call after obtaining a local address for the function within the client process by looking up the service procedure in an interface registry.

Abstract: A system in which a DHCP server executes a recovery routine after detecting a corrupted IP address state database. The routine determines whether an IP address is assigned to a DHCP client by querying an IP address/port reserved for DHCP clients. If the response suggests the absence of a DHCP client, the address is marked as BAD. If the response suggests the presence of a DHCP client, the IP database is updated appropriately. The query may comprise sending a TCP/IP packet to the IP address and port and monitoring for an ICMP error message. In another embodiment requiring a protocol extension, the DHCP server issues a DHCP supported query to each IP address that responds to a ping command. The DHCP clients supporting this protocol extension will respond to the query by returning all of the DHCP configuration information that was acquired before the IP address state database crashed.

Abstract: A system and method for converting 32 bit addresses into 64 bit addresses and enabling the 32 bit address to include a region index. The region index is stored in low order bits of the 32 bit address. In some architectures, namely the Intel IA-64 architecture, the low order bits are not used in entry point addresses because each entry point is on a 16 byte boundary. In the case of the IA-64 architecture, the low 4 bits of a 64 bit module entry point address are ignored. The region index in a 64 bit IA-64 address is stored in the high 3 bits of the address. Region index information is stored in the low order bits of the 32 bit address and copied to the high order bits for the corresponding 64 bit address. In this manner, the 32 bit address can include memory region index information without compromising the normal 4 gigabyte address space for a 32 bit address.

Abstract: A method and apparatus in a distributed data processing system for processing requests for documents. A request is received from a user for a selected page at a server. The selected page is returned to the user with a unique token, wherein each user is sent a unique token. Responsive to receiving a new request for a page, a determination is made as to whether the new request includes the unique token. Responsive to receiving the new request including the unique token, a determination is made as to whether a previous request from this user is simultaneously being processed by the server. Responsive to a new request having been received for a document while another prior request is pending, the new request is processed by either rejecting the new request, or by canceling the previous request and processing the new request, or by delaying the processing of the new request until the previous request has completed.

Abstract: A method and apparatus in a data processing system for managing receipt of data by a browser through a communications interface. Data is received at the browser through the communications interface using a portion of the bandwidth for the communications interface. Responsive to an input, a rate at which the data is received by the browser is reduced, wherein the portion of the bandwidth used to receive data is reduced.

Abstract: A processor includes instruction sequencing logic, execution circuitry, data storage coupled to the execution circuitry, and test circuitry. The test circuitry detects for a hardware error in one of the instruction sequencing logic, execution circuitry, and data storage during functional operation of the processor in response to an instruction within an instruction stream provided by the instruction sequencing logic. In one embodiment, a hardware error can be detected by comparing values output in response to a test instruction by redundant circuitry that performs the same function. Alternatively or in addition, a hardware error can be detected by performing an arithmetic or logical operation having a known result (e.g., multiplication by 1, addition of 0, etc.) in response to the test instruction.

Abstract: A system and method for including export information in the file system extended attribute data area is provided. File export information is determined by a system administrator or automated process. The determined export information is stored in an extended attribute data area corresponding with the file. When a computer system issues mount commands for the file systems to be mounted, the file system provides export information included in the extended attributes to the kernel whereupon the kernel exports the file system. Maintenance of file export information is thereby reduced. Backup, replications, and restorations of file systems is simplified by maintaining the export information along with the files being backed, replicated, or restored. For example, when the system administrator backs up a file, the export information in the extended attributes is backed-up as well. When the file system is retrieved, the export information is also retrieved within the extended attributes.

Abstract: An apparatus and method for communicating the completion of asynchronous I/O requests is provided. In particular, the apparatus and method make use of a new function call which is capable of waiting for a predetermined number of I/O requests to be completed prior to returning to the calling application. Control blocks for the I/O requests are updated after a predetermined number of I/O requests have been completed, i.e. in a process context rather than in an interrupt context as in the known systems. In this way, the overhead associated with known asynchronous I/O system calls is reduced.

Abstract: A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.

Abstract: A microprocessor and method of processing instructions therein are disclosed. Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence within the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor.

Abstract: A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline.

Abstract: A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle.

Abstract: An integrated circuit verification method and system are disclosed. The method includes generating a test description comprising a set of test cases. The functional coverage achieved by the test description is then determined. The functional coverage achieved is then compared against previously achieved functional coverage and the test description is modified prior to simulation if the test description achieves no incremental functional coverage. In one embodiment, generating the test description comprises generating a test specification and providing the test specification to a test generator suitable for generating the test description. In one embodiment, the test description comprises a generic test description and the generic test description is formatted according to a project specification and simulation environment requirements. If the coverage achieved by the test description satisfies the test specification.

Abstract: A method, system and program product for reassembling fragmented datagrams is described. A plurality of fragments of a plurality of datagrams are received by a recipient data processing system. In response to receipt of the plurality of fragments, a plurality of processes concurrently access a reassembly data structure to store the plurality of fragments, such that the plurality of datagrams are incrementally reassembled from the plurality of fragments. In one embodiment, the reassembly data structure can be implemented as a list containing a plurality of reassembly queues that each contain one or more queue entries for reassembling a respective datagram. Data integrity of the reassembly data structure can be maintained by associating a respective one of a plurality of locks with each of the plurality of reassembly queues so that only one process at a time can access each reassembly queue.

Abstract: A system and method for recovering data from parallel mirror drives following a system crash. During a parallel write to a mirrored disk array, it is unknown which of the disks comprising the disk array write the data to disk first. A completion array is used to record the first disk that stores a data item at a given address. During recovery from a system failure, the completion array is read to identify the last writes performed before the system failure occurred. The disk identified in the completion array is used as the master disk for the particular address identified. Data is read from that disk and address and propagated to the other disks in the mirrored disk array. Other items in the completion array may identify different disks to be used as the master for other addresses. In one embodiment, the completion array is stored in a reserved area of memory that is dumped to disk during a system failure and restored from disk during a subsequent system recovery.

Abstract: A method and system for establishing a priority order of threads executed within a multiprocessor data processing system are disclosed. The priority order of threads is maintained on a global queue within the data processing system and the queue is ordered by selecting a most favored runnable thread from among either a current thread, a favored thread, or an affinity thread. Once the thread is chosen, be it the current thread, the most favored thread, or the affinity thread, the chosen thread is removed from a run queue and then is run on the data processing system on a selected processor. An affinity thread pointer is updated to the thread being run to select the next affinity thread or the thread having the greatest affinity.

Abstract: A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer.

Abstract: Embedded links or hotspots in source Web pages are upgraded to reflect the new Universal Resource Locations (URLs) of moved target Web Pages. In a World Wide Web communication network with user access via a plurality of data processor controlled interactive display stations for displaying Web pages transmitted to receiving display stations from Uniform Resource Locations (URLs) remote from said stations, said Web pages being linkable with each other through embedded links in source Web page, a system is provided for updating said embedded links in source Web pages when the URL of a target Web page is moved.

Abstract: A graphical user interface is implemented with unique icons for registered but not mounted file systems, registered and mounted file systems, and mounted but not registered file systems. The unique icon for the registered but not mounted file systems permits management of such file systems by users within the network.