Abstract: A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer.

Abstract: Emergent information is created and utilized by an array of sensors. Each sensor is programmed with a trigger rule, which describes a local condition that must be met for the sensor to trigger an event signal, and a relationship rule, which describes a hierarchy of communication control among sensors in the array of sensors. When a predetermined percentage or weighting of the sensors trigger event signals, emergent information that describes conditions at the array location is generated.

Abstract: According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.

Abstract: A method for performing optical proximity correction with process variations considerations is disclosed. The maximum aerial gradient direction for a control point associated with an edge is initially determined. Then, a variational edge placement error E?along the maximum aerial image intensity gradient direction of the control point is calculated. A determination is made whether or not |CE·n| is equal to or greater than a manufacturing grid, where n is the direction perpendicular to a segment pointing outward, and C is a constant. If |CE·n| is equal to or greater than a manufacturing grid, the edge is moved by ?CE·n.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

Abstract: A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.

Abstract: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.

Abstract: A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.

Abstract: A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion.

Abstract: A technique for installing a heatsink in an electronic assembly includes simultaneously applying force to multiple fastener assemblies that each retain a respective fastener in a body of the heatsink. The heatsink is then attached to the electronic assembly by actuating the fasteners while the force is simultaneously applied to the multiple fastener assemblies.

Abstract: A method for providing access control to a single sign-on computer network is disclosed. A user is assigned to multiple groups within a computer network. In response to an access request by the user, the computer network determines a group pass count based on a user profile of the user. The group pass count is a number of groups in which the access request meets all their access requirements. The computer network grants the access request if the group pass count is greater than a predetermined high group pass threshold value.

Abstract: A method for exchanging information between computers from different computer networks without any direct connection is disclosed. The two networks include corresponding bridge computers that which share a file system residing on a common storage device. Any computer of a network needing to transmit information to a computer on the other network can map the file system of the corresponding bridge computer. The computer authenticates itself on the bridge computer, and it is then allowed to write the information into a file residing on the shared memory device. Likewise, any computer on the other network can map the same file system of the corresponding bridge computer. The computer authenticates itself on the bridge computer, and it is then allowed to read the information from a mirror copy of the file on the shared memory device. As a result, any network that is isolated from the outside can send and receive information.

Abstract: An improved method and system for manipulation a plurality of graphical pointers utilizing a single graphical pointing device are disclosed. A plurality of graphical pointers are displayed within a display device. A user may then temporarily select one graphical pointer among the plurality of graphical pointers. During the selection, the selected graphical pointer is manipulated in response to operation of a single graphical pointing device. A point within the display device specified by the position of the selected graphical pointer is selected in response to closure of a switch associated with the selected graphical pointer.

Abstract: A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).

Abstract: A technique of detecting an open integrated circuit (IC) pin includes selectively coupling a first open detect circuit, which includes a first inverter having a first threshold, to the IC pin. Next, a first logic state at an output of the first inverter is determined. Then, based upon the first logic state, it is determined whether the IC pin is open or whether it is indeterminate as to whether the IC pin is open. When it is indeterminate as to whether the IC pin is open, based on the first logic state, a second open detect circuit is selectively coupled to the IC pin. The second open detect circuit includes a second inverter having a second threshold (the first threshold is greater than the second threshold). A second logic state at an output of the second inverter is then determined. Finally, based upon the first and second logic states, it is determined whether the IC pin is open.

Abstract: Blind modulation detection in a receiver of a wireless communication device calculates error energies for PSK and GMSK based on differences between a received training sequence signal and synthesized training signals generated from PSK and GMSK channel estimations and a known training sequence phase rotated by 3?/8 and ?/2 per symbol, respectively. A highly reliable modulation detection in a Single Antenna Interference Cancellation (SAIC) operational environment is achieved by a dual comparison of a total energy value of the received signal and the two error energies. PSK is determined if the PSK error energy value is found to be lower than both the GMSK error energy value and the total energy value by predetermined thresholds; otherwise the modulation type is determined to be GMSK.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A storage controller (104) for a storage system (100) in which there are multiple storage devices (109) and a method for recording diagnostic information are provided. The storage controller (104) includes a storage device manager (203) which has means for allocating a storage device (109) in the storage system (100) for storing diagnostic data. The storage controller (104) also includes means for generating diagnostic data regarding the operation of the storage controller (104). Two buffers (207, 208) are used for alternately recording and writing batches of diagnostic data to the allocated storage device (109). The allocated storage device may be a storage device which is normally reserved for disaster recovery in the storage system (100).

Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.