Abstract: An optical storage arrangement is provided where a unified optical disk, or other optical media, has separate Read/Write (R/W) and Write Once Read Many (WORM) areas. A Read/Write head or transducer selectively records data only once in the WORM area but records and re-records data in the R/W area. Both areas can be selectively read repetitively. The WORM area is used to store data records and the R/W area contains directories for the data records recorded in the WORM area.

Abstract: Workstations are connected via workstation controllers to two computer systems where one of the workstation controllers is a primary or controlling workstation controller and the other workstation controller is connected to appear to the primary workstation controller as a workstation and is designated as the secondary or standby workstation controller. The standby workstation controller has its line impedance matching resistor connected to function as a line terminator but it can also function as a line driver resistor when the primary or controlling workstation controller fails, the failure of the primary or controlling workstation controller being detected by the secondary or standby workstation controller upon the failure of being polled by the primary or controlling workstation controller within a predetermined period of time. The line impedance matching resistor of the failing primary or controlling workstation controller then functions as a line terminator resistor.

Abstract: High frequency transmitter and receiver circuits are AC coupled for party line transmission over coaxial cable where the circuits are connectable to the cable by use of stinger taps and thereby eliminate the need to interrupt service when connecting the circuits to the cable. The transmitter circuit includes oppositely polled current sources which are alternately switched to the coaxial cable via the stinger tap or to a dummy load by current switches connected to data inputs via buffer circuits. A transmit enable circuit controls the current sources to be active or inactive and to prevent unbalances from saturating either current sources. The receiver includes a high input impedance biasing network and buffer amplifier that maintain the high input impedance even when power is off. Capacitance at the tap is reduced by a capacitor drive circuit which feeds input signal back to transmitter blocking diodes and to the trunk tap.

Abstract: A scanner for scanning an increased area of a finger held or pressed on a concave elliptically cylindrical surface having two focal axes includes a linear light source positioned at one focal axis of a first reflective cylindrical elliptical surface, the other focal axis coinciding with one focal axis of the concave elliptical surface in contact with the finger. A second reflective, cylindrical elliptical surface has two focal axes where one of the axes coincides with the position of a linear array combination of photosensitive elements and charged coupled devices and the other coincides with the other focal axis of the concave elliptical surface in contact with the finger.

Abstract: Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected to the external interface between the central processing unit (CPU) and main storage and converted to a virtual address. The virtual address is compressed and entered into a large buffer via buffer control logic. The buffer control logic sends a signal to stop the CPU when the buffer becomes full and restarts it at the exact point it had stopped after the buffer has been emptied by the transfer of data from it to a slower speed storage device.

Abstract: An I/O device control subsystem for controlling issuance of commands to one I/O device while it is doing I/O device to I/O device data transfers with another I/O device. The I/O device control subsystem has a timer for indicating current time. The time required to write the transferred data, known at the time the data transfer command is issued, is added to the current time. Then, when a command is issued to the first I/O device while the other I/O device is writing the transferred data, the time required for executing that command is determined as well as the time remaining for completion of the write operation and if the time required for execution of the new command is less than the remaining time, the new command is allowed to be executed.

Abstract: Extended control word decode circuitry increases the number of simultaneous functions performed during execution of a control word in the central processing unit (CPU) of a computer system. A first field of a control word is decoded into 2.sup.n decodes for testing or specifying a first set of CPU conditions. A second field in the control word is decoded into 2.sup.m -X decodes for testing or specifying a second set of CPU conditions. The X decodes, which together with the 2.sup.n decodes of the first field test or specify multiples or pairs of a third set of CPU conditions and inhibit the 2.sup.n decodes from testing or specifying said first set of CPU conditions.

Abstract: A method and apparatus are provided to enable interruption of list processing operations in a computer system and to enable restart from the point of interruption. A mechanism, at a predetermined point of the list processing operation, operates to recognize occurrences of interrupting events. If any such events are present, a mechanism saves the status of the list processing operation, saves the identification of the task associated with instruction executing the list processing operation and locks the list or queue. After the interrupt is handled, a mechanism restores status, and unlocks the list or queue only when the identified task is active again and the instruction which had been executing the list processing operation is again executing.

Abstract: An oil-based corrosion inhibitor containing an aliphatic amine, a fatty acid and its ester, and an organotin compound provides improved corrosion resistance to metals and is easily removed when the metals are to be processed.

Abstract: A method for evaluating boolean expressions includes steps of forming a first vector for selecting and conditioning the boolean variables prior to their evaluation and forming a second vector for specifying logical AND and OR operations in the normal form of the boolean expression. Evaluation of the boolean expression is then performed by translating the first vector using the boolean variables as a translate table. The result of the translation is logically combined with the second vector using an exclusive OR function. The result of the exclusive OR operation is translated with and upon itself and the state of the last position of the result of this translation is the result of the evaluation of the boolean expression.

Abstract: Thermoplastic materials are joined to non-thermoplastic materials such as thermosetting materials by laser radiant energy which causes the thermoplastic material to flow onto the thermosetting material, preferably into a notch or groove or over a shoulder or lip to form a joint by mechanically locking the materials together.

Abstract: Task dispatching for an asymmetric or symmetric multiprocessor system is provided where all the processors are dispatched from a single task dispatching queue. The workload, i.e. tasks, of the multiprocessor system is distributed to the available processors. Each processor includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.

Abstract: A line printer attachment for converting a display screen copier printer to a line printer. The last or extra line of the display is used as the line print buffer. An initiate print signal is generated upon detecting that the last or extra line is to be scanned. The initiate print signal is used to blank or inhibit the serial video data from the display screen and to enable the printer. The serial video data is constantly sent to the printer attachment but is ignored until the printer is enabled. With the printer enabled, printing takes place using the line print buffer data which has been serialized as serial video data. The print buffer data remains unchanged during the entire printing of the line where the printing is done in series of horizontal lines to complete the printing of a line. At the end of each horizontal line of print a vertical screen retrace occurs and the display screen is swept where again the last or extra line is detected and another initiate print signal is generated.

Abstract: An apparatus is provided for assembling information concerning the occurrence of a channel error to form a channel error event consisting of four fields: a channel function field; a field identifying the I/O register in use at the occurrence of the channel error; a field identifying the particular I/O adapter using the channel when the error occurred; and a field specifying the type of channel error. The four-field channel error event is placed in an I/O event stack accessible to the CPU, and the CPU is notified of the addition to the I/O event stack. If the attempt to store the channel error event on the I/O event stack fails, the channel is stopped until the CPU signals the channel to restart and to again attempt to log the channel error event on the I/O event stack.

Abstract: A system for controlling the cycle time of a central processing unit having associated control store memory units for the storage of information is provided. The system includes a plurality of control store memory locations disposed within the control store memory units for the storage of information. A plurality of control store memory locations are operable at varying speeds and are accessible by the central processing unit. Circuitry is provided for addressing one of the plurality of control store memory locations responsive to address information contained within the information stored within the plurality of control store memory locations. The addressed information selects the next successive control store memory location to be addressed by a central processing unit.

Abstract: Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations, it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.

Abstract: A computer system having two processors and storage where storage is segmented so as to permit simultaneous access by the two processors with the address path of one processor being limited to a particular segment of storage so as to eliminate contention in other segments. One processor can address all segments of storage and place processed data into and retrieve data from the segment of storage accessible by the other processor. This eliminates the need for cycle stealing because the other processor can access processed data or store data while the one processor simultaneously accesses another segment of storage. Storage contention is resolved on the basis of addressing. If both processors are simultaneously trying to address the same segment of storage, the processor which can address all segments of storage is granted the access.

Abstract: Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address in an I/O resolved address register reserved (unique) to the commanded I/O device connected to a shared I/O control unit and to repeat such an operation for each I/O device commanded by the CPU to do a data transfer and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into I/O resolved address registers shared for use by all of I/O devices whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer

Abstract: Improved task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.