Abstract: Control circuitry is provided for controlling the generation of a block check word simultaneously with the writing of control words into a transient area of a writeable control storage. The control circuitry in response to a write control storage instruction generates control signals for controlling existing central processing unit (CPU) hardware to effect generation of the block check word while a control word is being written into the transient area of control storage. Microinstructions in the resident area for performing the overlay force selection of a local storage register which has been initialized. The operand from the local storage register is applied to the ALU together with the word which is also being written into control storage. The ALU is forced to perform an exclusive OR operation and the result is returned to the selected LSR. In this manner a block check word is dynamically calculated word by word as each word is written into control storage.

Abstract: Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated.

Abstract: Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms.

Abstract: Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table.

Abstract: Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

Abstract: A register control instruction is added in a stored program computer and uses the same OP code as used for an existing storage instruction. A non used bit state in the existing storage instruction identifies the instruction as a register control instruction rather than a storage instruction and causes logic to generate a control signal for inhibiting the storage operation whereby the storage address is used for addressing a register instead of storage and data is transferred to or from the addressed register as per other control information in the instruction. The bit state identifying the instruction as a register control instruction is converted to a used bit state of the storage instruction so as to invoke an address update operation normally invokable by the storage instruction to update the storage address used instead for register addressing.

Abstract: Instruction processing rate in a computer system is increased by providing a high speed data path to central processing unit (CPU) registers and including an auxiliary arithmetic and logic unit to enable updating the instruction address register (IAR) in one operation concurrently with a storage fetch whereby two storage fetches can be made within a single machine cycle. Normal instruction rate processing is retained by generating idle or dummy half cycles to enable a single storage fetch per machine cycle and thereby maintain flexibility for I/O instruction processing, for diagnostic purposes and for fetching the last byte or segment of an instruction having an odd number of bytes or segments.

Abstract: Storage protection is provided in a computer system having address translation by loading address translate registers with valid translated addresses and with special addresses. A circuit for generating a storage exception signal is connected to receive all addresses from the translate registers which are addressed by the main storage address and generates a storage exception signal in response to detecting a special address. The address translation mode is provided for both a main storage processor and a control processor with a separate address translate control register for each processor. Address translation is automatically selected based upon interrupt level. Address translation registers are also provided for I/O operations and are controlled independently from and can be in parallel with the task address translation registers.

Abstract: An asymmetrical multiprocessor system has a main storage or macroprocessor connected under control of a microprocessor for initiation and termination of operation of the macroprocessor. The macroprocessor after being started by the microprocessor runs until a check condition in the macroprocessor occurs, a non-executable operation code (OP code) in the macroprocessor is encountered, or the microprocessor wants control. When the macroprocessor stops the microprocessor is interrupted. The interrupt routine handles the condition causing the interrupt and restarts the macroprocessor. Non-executable OP codes include supervisor call and invalid OP codes. I/O operations are handled by the supervisor call instruction.

Abstract: A common reliability and serviceability (RAS) bus is connected to each functional combination of LSI apparatus, i.e., storage control, central processing unit (CPU), input/output (I/O) attachments and devices, and system control adapter constituting a computer system. The common RAS bus includes a unique address line to facilitate discrete addressing of each functional unit from the system control adapter. Logic is included in each I/O type of functional unit which is responsive to the address signal and a test mode signal for degating or blocking data normally transferring between the functional units.Other logic provides control signals for causing the addressed functional unit to go thru one clock cycle, one shift cycle, one machine cycle or one instruction cycle. This enables the addressed unit to go thru an operation after a test pattern has been loaded into the functional unit while the system continues to operate concurrently, if the addressed unit is other than the CPU.

Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place.

Abstract: The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.

Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.

Abstract: A computer system executes instructions for an I/O device not attached to the system. A quasi I/O attachment device is responsive to the commands for the unattached I/O device and generates an interrupt condition. The interrupt condition causes the command instructions for the unattached I/O device to be translated to command instructions for an I/O device connected to the computer system. The I/O device attached to the system performs the designated operation and generates associated I/O device status data. This associated I/O device status data is translated into I/O device status data for the unattached I/O device and thus permits a program for operating an unattached I/O device to operate instead an I/O device attached to the system which otherwise could not be operated by that program. A second embodiment performs the emulation of the unattached I/O device remotely of the central processing unit in the computer system.

Abstract: Small current signals (0.5 ua and less) such as the output of a photodiode are direct current coupled to a preamplifier which also passes an impedance reducing injection current to a pair of amplifiers. A voltage output proportional to the logarithm of the signal current is produced by passing the amplified current through a log producing junction of a transistor. However, to produce the logarithm function accurately, the injected or impedance reducing current is precisionally removed so that only a very minute portion (one part out of 5000) passes through the log producing junction.

Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.