Abstract: A dial tone detection arrangement for a PBX which provides a dial tone detection notification feature to a calling party is disclosed. The disclosed arrangement relieves the calling party from the burden of aurally monitoring the receiver of a station while waiting for receipt of central office (C.O.) dial tone. The dial tone detection notification feature is advantageous under conditions where the calling party places a call to a called station served by the C.O. and experiences extensive delays, e.g. 30 minutes, in the receipt of C.O. dial tone. The dial tone detection arrangement utilizes an algorithm to establish a connection between a dial tone detection circuit of the PBX and a trunk port connected to a C.O. via a switching network. The dial tone detection circuit monitors the C.O. via the trunk port for the presence of dial tone indicative of C.O. availability. The calling party may now go "on-hook" and await a notification at the calling station indicative of the detection of dial tone.

Abstract: A timing control arrangement that dynamically controls the distribution of iming information in a distributed digital communication system. A reference timing signal is distributed from a reference master node to all other nodes in the system. The distribution is accomplished on a dynamic basis without the use of a central control. Each node is connected by links to at least one other node and each node receives timing signals from all of the links to which it is connected. Each node selects one of these signals as its timing reference by scanning the various signals it receives to identify the one signal that is applied via a link path that is the "closest" to the master reference node as indicated by information specifying the number of intermediate nodes through which the timing signal has traveled from the reference node to reach the receiving node.

Abstract: Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not currently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.

Abstract: A data transmission flow control arrangement for controlling the flow of data packets to a network as tramsmitted by one or more data transmitting and receiving devices via an interface is disclosed. The disclosed flow control arrangement provides circuitry in the interface responsive to the storage capacity of a buffer included in the interface. If the buffer contains sufficient space to store a data packet of maximum length, data transmissions continue unencumbered. However, if the buffer contains insufficient space to accomodate a data packet of maximum length, the specialized circuitry of the interface responds to this condition and applies a signal to all of the associated transmitting and receiving devices of the interface. The jamming signal simulates the conditions associated with a busy network and therefore, inhibits the transmission of data from any of the associated transmitting and receiving devices.

Abstract: A packet switching system is disclosed for transmitting variable length packets between system ports. Each byte of each packet has a special one-bit field for indicating whether the byte is the last byte of a packet. A "1" in this field specifies that the byte is the last byte of a packet and activates port control circuitry that changes the potential on a system control conductor to indicate that the system data bus is now idle and free for use by other ports.

Abstract: Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve the circuit switch information or the packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus.

Abstract: A clock recovery circuit for recovering the clock from an incoming data stream. The circuit comprises a transition detector and a module 3 counter operating at three times the expected rate of the incoming clock. A clock pulse is generated by the counter one count interval after a transition is detected.

Abstract: The disclosed PBX integrity arrangement utilizes a specialized processing operation to provide an integrity check for communication devices and trunk facilities connected to a PBX. The integrity check determines (1) whether a user of a device or a trunk facility is permitted access to one or more PBX operations or (2) whether the PBX operation meets expected conventional PBX call establishment conditions. If access is prohibited or an atypical condition is present, this access or condition may indicate permission tampering, device or trunk facility misuse, malfunction or unauthorized PBX user activity. The occurrence of any one of the above conditions produces an immediate response which either remedies the occurrence or provides notification of the occurrence of the condition to a PBX administrator.

Abstract: Improved alternate routing in a packet switching system is provided by inserting alternate routing control information into each packet and by storing alternate routing information at each network node. The stored information at each node includes a list of the available paths extending from the node towards all other nodes together with a list of available algorithms that can be used to select one of the available routes. The alternate routing control information in each packet contains postage information specifying the maximum number of nodes through which the packet is to travel. The alternate routing control information also includes a destination node index code identifying the destination node. The destination node index is used as address information by each node receiving a packet to read out the stored information at the node identifying the available paths and the algorithm to be used in selecting one of these paths for use in transmitting the packet towards the destination node.

Abstract: A flow control mechanism for a packet switching system that provides for the continuous dynamic control of station window size beginning with call setup and extending through the duration of the call. A station window size can be of a first magnitude at call setup time when system traffic may be low. The window size can be subsequently reduced to free up port buffer space as system traffic increases. This permits the serving of more calls during periods of heavy traffic.

Abstract: Presently available printed wiring board backplanes used in switching systems and the like are wired at the time of manufacture to enable only a fixed number of groups of circuit boards to communicate with each other. This limitation prevents a backplane from having the capability of serving a varying number of groups of boards. The present invention enables a backplane to have the capability of serving a variable number of groups of boards. The number of groups that can be served by a given backplane need not be fixed when the backplane is designed and manufactured. Each backplane of the present invention comprises backplane bus conductors and board conductors. The boards are effectively a part of the bus. The use of a first type of board in a backplane connector continues the bus to the adjacent connector. The use of a second type of board terminates the bus and does not extend it beyond the connector into which the second type of board is inserted.

Abstract: A packet switching system having separate arbitration and data buses together with circuitry for dividing the buses into a plurality of time segments termed phases. The plurality of phases permit a like plurality of separate arbitration operations and a like plurality of separate data exchanges to be effected concurrently on the arbitration bus and data bus, respectively. The use of n phases increases the data transmission capability of the system by a factor of n over prior art arrangements using only a single phase.

Abstract: Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

Abstract: A flexible organizing sleeve device for ordering a plurality of elongated members such as wire and/or cables. The sleeve comprises at least two sheets of flexible material having substantially the same dimensions of width, length and thickness. The interior facing surface of each sheet has attached thereto a plurality of resealable parallel mating strips running substantially along the length of the sleeve. To install the device, a user mates the first pair of parallel mating strips and places a wire, for example, next to the mated strips between the sheets. A user then mates the next consecutive pair of parallel mating strips. The wire is now contained within a compartment-like structure. The user simply repeats the mating process of forming separate and individual compartments for each wire until the entire organizing sleeve is filled and the plurality of wires are ordered.

Abstract: A control circuit for receiving clock signals from duplicated sources, such as a pair of Time Slot Interchanges (TSI) and for normally extending the clock signal of the on-line source to clock signal utilization devices, such as digital port boards. The control circuit contains circuitry which ensures that no spurious pulses are applied to the port boards when the TSIs interchange their on-line/off-line status.

Abstract: A distributed packet switching system in which a centralized switch is not used and, instead, each transmitting port contains the intelligence required to derive and then insert the destination port and station addresses into the header of each packet to be transmitted by the port. The port circuitry that derives the destination addresses operates under control of a central controller which, prior to the setup of each call, receives information identifying the transmitting port and calling station as well as the destination station number dialed at the calling station. The controller processes this data to derive the destination port and station addresses. The derived addresses are sent to and stored in a RAM in the transmitting port. The RAM outputs the destination port and station addresses for each packet subsequently transmitted by the port on the call.

Abstract: A diagnostic test facility for a processor having a plurality of boards hierarchically arranged with respect to processor function.The first and most independent board contains the processor microstore that stores the usual information plus the processor diagnostic subroutines required to test all boards. The processor is tested by executing the diagnostic subroutines associated with the first board and by collecting and comparing test data with predicted data as the subroutines are executed. The second board is tested by using the facilities on the first board and by executing diagnostic subroutines associated with the second board. In a similar manner the remaining hierarchically arranged boards are tested in sequence with the testing of each board using the circuitry on the priorly tested boards.

Abstract: This telephone switching system is comprised of a plurality of time slot interchangers (TSIs) which exchange information on an interleaved basis. The TSI's write and read this information in their associated port data store memories using common buses on a time shared basis. The interleaving permits faster call processing since the data store operates faster than its associated TSI and can therefore respond to read/write requests from a number of TSI's. The interleaving also permits each TSI processor to serve only certain types of calls, wherein each TSI may be equipped with a specialized processor adapted to serve a unique type of call such as conference, nonconference, data, etc.

Abstract: Protocol support and message buffering circuitry is used to transmit call status, control and terminal management information bidirectionally over associated conductor pairs as signalling messages between a system processor and a phone and/or terminal served by the system and connected to each conductor pair. This information is transmitted serially in a modified HDLC format as a one bit signalling field of a multiplexed data frame. At each transmitting end, the message information is converted from a parallel to a serial format, transmitted serially as the signalling bit of successive frames, and reconverted to parallel at the receiving end.Ports terminate the system end of the conductor pairs and are mounted four to the board. Each board contains circuitry, such as registers and the like, common to the signalling message protocol support and message buffering circuitry of all four ports.

Abstract: A PCM switching system requires the assignment of either one or two time slots of a pair of time slots to a port circuit depending upon the type of service (voice only or voice plus data) each port circuit provides. Common resources normally assign a pair of time slots to each port circuit. This wastes time slots when the port circuit is used in a manner (voice only service) that requires only a single time slot. The disclosed arrangement eliminates the wasting of time slots by permitting the on-site reconfiguring of the system resources so that, when desired, only a single time slot can be assigned to a port circuit.