Abstract: Circuitry allocates requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. Increased flexibility in port preference is provided by the use of a plurality of status flip-flops in each port for generating dynamic port parameter bits. The generated parameter bits are normally applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to prevent any parameter bits from being applied to the bus as long as the mask signal remains.

Abstract: An arrangement for according station and attendant feature transparency between independently operational PBXs of a PBX network. Each PBX includes a switch processor, station lines and tie-trunks extending to other PBXs. Each PBX also has a Direct Memory Data Controller (DMDC) for transmitting service or feature related data messages associated with tie-trunk calls to other PBXs over data links. On an interPBX call, the DMDC in a calling PBX transmits a data message to a DMDC in the called PBX over a direct link between the calling and called PBXs. In the event there is no direct link between the calling and called PBXs, the DMDC in the calling PBX transmits a message over a data link to a DMDC at a tandem PBX which, in turn, sends the message over a link to a DMDC in the called PBX.

Abstract: A programmed controlled signal processor operating as a time slot interchanger and having improved conferencing facilities is disclosed. A conference accumulator RAM is used that has a memory location unique to each conference call served by the system. A unique RAM location is assigned to the serving of each conference call in order to facilitate the generation of the required sum and difference signals. The use of an individual accumulator RAM position for this purpose permits the use of a simpler instruction set for the signal processor. This simpler instruction set permits a plurality of instructions for the serving of a given conference call to be interspersed with instructions for other calls rather than be contiguous to one another.

Abstract: Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of requesting ports. During bus contention time, each requesting unit synchronously and sequentially applies the digits of its unique priority code to the bus beginning with the most significant digit. Each requesting unit remains in contention only so long as each digit it applies is greater than or equal to the digit applied by any other unit. After the application of all digits, only the requesting unit having the highest code remains in contention and it seizes the bus. A polarity control conductor is provided, selectively altering the preference that is normally specified by the assigned priority codes. The application of a reversal signal to this conductor for a given interval of time causes each requesting unit to invert each bit of its priority code it applies to the bus during this time interval.

Abstract: Circuitry is disclosed for allocating requests for demand-shared bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. A plurality of status flip-flops is provided in each port for generating port parameter bits. The generated parameter bits are applied to the bus as the most significant bits of a dynamic port priority code during contention time. However, the selective application of a mask signal to a mask conductor during contention time causes each requesting port to ignore any parameter bits on the bus as long as the mask signal remains. This returns control of the port preference to any unmasked parameter bits and to the assigned port priority codes.

Abstract: Circuitry is disclosed for allocating requests for demand-sharing bus access among a plurality of service requesting ports. During bus contention time, each requesting port synchronously and sequentially applies the digits of its assigned unique priority code to the bus beginning with the most significant digit. After the application of all digits, only the requesting port having the highest code remains in contention and it seizes the bus. The present invention provides flexibility in port preference by the use of a plurality of status flip-flops in each port for generating dynamic port parameter bits. The generated parameter bits are normally applied to the bus as the most significant bits of a dynamic port priority code during contention time. The state of the status flip-flops is controlled by circuitry which counts the number of packets of a specified size currently stored in the buffer memory of each port.

Abstract: A semiautonomous digit collection and call state detection subsystem is provided for use in a time division switching system such as a PBX. Each active (call serving) system port circuit applies a hook state signal to a specially provided bus during each occurrence of the time slot to which the port circuit is assigned. The subsystem's logic analyzes these hook state signals to identify certain predetermined call states and to count dial pulses. Output messages representing identified call states and dialed digits are made available to the switching system under control of a system scanner.

Abstract: Processor circuitry is disclosed for setting a memory address register to a predetermined address upon the receipt of an interrupt request. The receipt of the request extends a steady state signal through an AND gate to the input of the counter to hardwire jam it to a predetermined address which defines the memory location of the first word of a subroutine associated with the request. The jam signal remains on the register input until the addressed memory location is read out. A readout of this location disables the AND gate and removes the jam signal from the counter. The AND gate is restored to normal when the last word of the subroutine is read out to permit new interrupt requests to be honored. The continuous application of the jam signal to the register until the addressed location is read out increases the probability of the register being successfully set to the correct address.

Abstract: A processor is disclosed having improved circuitry for (1) generating m+n-bit address words from n-bit data words and (2) converting m+n-bit address words back into data words having an n-bit format. The processor includes a first arithmetic unit (AMU) that is n bits wide and which receives n-bit words from a data bus. The processor further includes a second AMU that is m bits wide and which is connected to receive the m least significant bits of an n-bit word stored in the first AMU.

Abstract: A multiprocessor system having a computer poller and a memory poller for controlling information transfer over a time multiplex bus between a plurality of computers and an interleaved memory comprising a plurality of sections. Each poller comprises a counter and a clock so that as the counter is incremented by the clock, each computer or memory section, respectively, is sequentially interrogated to determine whether or not it requires access to a memory or computer, respectively.

Abstract: A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to detect the receipt of each address word representing a defective ROM locaton. Upon each detection of a defective address, the decoder temporarily inhibits the output of the ROM and causes a small auxiliary memory to output valid program information as a substitute for that in the defective ROM location. A counter is used as a supplemental addressing source for both the decoder and the auxiliary memory. This increases the patching capability by subdividing the decoder and the auxiliary memory into 2.sup.n segments where n is the number of bits supplied by the counter.

Abstract: A read only memory (ROM) patching arrangement is disclosed which provides valid output information whenever ROM locations containing invalid information are addressed. The disclosed arrangement detects the receipt of each ROM address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary PROM to output valid information as a substitute for that in the defective ROM location. Decoder circuitry is disclosed which uses a minimum number of small capacity PROMs to detect a limited number of ROM addresses to be patched.

Abstract: A ROM patching facility is disclosed which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The disclosed equipment repatches one or more times a ROM address that has already been patched. Upon the detection of each such address, the program information associated with the most recent implemented patch is returned to the system. The disclosed equipment comprises a plurality of PROM decoders for detecting ROM addresses that are to be patched and for generating output signals representing each patched address, encoders for receiving the decoder output signals and for encoding each such signal into binary address information, and auxiliary memories controlled by the encoder address information for providing valid program information to the system upon each detection of a patched ROM address.

Abstract: A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever defective ROM word locations containing invalid information are addressed. The disclosed arrangement, which includes a decoder comprising a plurality of small capacity PROMs, detects the receipt of each address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary memory to output valid information as a substitute for that in the defective ROM location. The patching capability of the auxiliary memory and the decoder PROMs is increased by extending n bits of each ROM address word to n inputs of the auxiliary memory as well as to n inputs of each decoder PROM. The remaining inputs of the decoder PROMs, taken collectively, each receive a different one of the remaining bits of each ROM address.

Abstract: A shift and rotate circuit is disclosed for a processor which receives 16-bit words as input data, which breaks down each received word into four 4-bit bytes, and which performs logical and arithmetic operations on each word on a byte-by-byte basis. A word is shifted a specified number of bit positions (1) by entering the word byte-by-byte in consecutive locations of a first 4-bit wide memory, (2) by entering the same word in an ordered byte sequence in a second 4-bit wide memory with the ordered sequence being determined by the number of bit positions the word is to be shifted, and (3) by concurrently applying the contents of both memories byte-by-byte to the shift and rotate circuit which shift the received information to the required number of bit positions and writes the shifted information into consecutive locations of the second memory. The 4-bit bytes of the shifted word are ultimately reconstituted into a 16-bit word and outputted onto the I/O system.