Patents Represented by Attorney, Agent or Law Firm Donald R. Boys
  • Patent number: 7376954
    Abstract: A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first scheduler that consults the register to assign issue slots to the context. The first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: May 20, 2008
    Assignee: MIPS Technologies, Inc.
    Inventor: Kevin D. Kissell
  • Patent number: 7280548
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: October 9, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Patent number: 7257814
    Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: August 14, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Stephen Melvin, Mario Nemirovsky
  • Patent number: 7237093
    Abstract: In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and a hit/miss predictor for forecasting whether a load instruction will hit or miss the cache. The prediction by the hit-miss predictor is used by the fetch algorithm in determining from which stream to fetch. A hit prediction results in a next instruction being fetched from the same stream as the instruction tested by the hit/miss predictor, while a miss prediction results in the next instruction being fetched from a different stream, if any. The predictor is also used to determine which instructions to dispatch to functional units.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: June 26, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Enric Musoll, Mario Nemirovsky
  • Patent number: 7197043
    Abstract: A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: March 27, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Enrique Musoll, Mario Nemirovsky, Stephen Melvin
  • Patent number: 7165257
    Abstract: A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: January 16, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Enrique Musoll, Mario Nemirovsky, Stephen Melvin
  • Patent number: 7155516
    Abstract: A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storage system to store packets in the EPM. The system is characterized in that the first storage system attempts to store all incoming packets in the LPM, and for those packets that are not compatible with the LPM, relinquishes control to the second system, which stores the LPM-incompatible packets in the EPM.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: December 26, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Patent number: 7139898
    Abstract: A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: November 21, 2006
    Assignee: Mips Technologies, Inc.
    Inventors: Mario Nemirovsky, Adolfo Nemirovsky, Narendra Sankar, Enrique Musoll
  • Patent number: 7139901
    Abstract: A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: November 21, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Enrique Musoll, Mario Nemirovsky, Stephen Melvin
  • Patent number: 7103046
    Abstract: In a network node having one or more packet processors and at least one CPU required to process specific types of packets, a system for managing the specific types of packets for CPU processing has one or more packet processors enabled to sort the specific types of packets into two or more categories of different priority for processing; and a queue set for queuing the sorted packets according to priority ahead of the CPU. The system is characterized in that the CPU processes the queued packets according to priority. In a special case the queues are a part of network access controller (NAC). Also in some cases a software component is provided for configuring the hardware.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 5, 2006
    Assignee: Pluris, INC
    Inventors: Russell R. Tuck, III, Puneet Agarwal
  • Patent number: 7065096
    Abstract: A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: June 20, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Enrique Musoll, Mario Nemirovsky, Stephen Melvin
  • Patent number: 7042887
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: May 9, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Patent number: 7035997
    Abstract: In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch. In some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: April 25, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Enric Musoll, Mario Nemirovsky
  • Patent number: 7035998
    Abstract: A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for individual streams in each cluster, a first dedicated dispatch stage in the first cluster for dispatching instructions to execution units, and a second dedicated dispatch stage in the second cluster for selecting and dispatching instructions to execution units. The processor is characterized in that the clusters operate independently, with the dedicated dispatch stage taking instructions only from the instruction queues in the individual clusters to which the dispatch stages are dedicated. In preferred embodiments there are dedicated fetch and dispatch stages for streams in the clusters, and dedicated execution units to which instructions may be dispatched.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: April 25, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Stephen W. Melvin, Nandakumar Sampath, Enrique Musoll, Hector Urdaneta
  • Patent number: 7032226
    Abstract: A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 18, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky, Enric Musoll
  • Patent number: 6848453
    Abstract: An ornamental toothpick system has a toothpick and an ornamental extension having a body with an outer surface comprising one or more of a specular finish, ornamental indicia or text, and an engagement interface engaging the ornamental extension to the toothpick.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: February 1, 2005
    Assignee: Sound Starts, Inc.
    Inventor: Christian Kite Hampton
  • Patent number: 6842782
    Abstract: A software tool for enabling automated tracking of activity related to the status and usage statistics of a plurality of Web sites on a data packet network is provided. The software tool comprises a network communication capability for establishing network communication between the software tool and the tracked Web sites; a plurality of data-reporting modules for obtaining and reporting data about tracked Web sites; a data input function for excepting data from the reporting modules and from external sources; a data recording function for recording and logging the data received from the reporting modules and from the external sources; and a data management function for organizing and storing the received data and rendering the data accessible for use in software development.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: January 11, 2005
    Assignee: Yodlee.com, Inc.
    Inventors: Masroor Malik, Naveen Venkata Akunuri, Christoph Kern, Tim Armandpour, Sam Khavari, Ganesh Narasimhan
  • Patent number: 6839675
    Abstract: A digital processing system for monitoring sound effects produced by codecs during a signal processing session is provided. The digital processing system comprises, a sound source for producing signals for processing, a sound monitor having at least two channels for monitoring sound quality of the sound source, a sound recorder for recording the sound source, a playback device for playing a recorded file of sound produced by the sound source, a codec simulator for simulating sound effects produced by codecs, a plurality of codecs for compressing and decompressing sound files and a control interface for sampling, adjusting, and implementing an optimum codec based on monitoring of sound effects produced by codec simulation. A user controlling the system may monitor sound variances produced by any one of the plurality of codecs affecting the quality of sound from the sound source during signal processing of the source sound without interruption of the signal-processing session.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: January 4, 2005
    Assignee: Euphonix, Inc.
    Inventors: Robert Denton Silfvast, Philip J. E. Campbell, Scott Silfvast, Andor Izsak, Paul deBenedictis, Steven H. Milne
  • Patent number: 6832634
    Abstract: A system for carbonating a liquid with carbon dioxide gas comprises a pressurized source of carbon dioxide gas, a user-operable three-way valve system having a first, a second, and a third orifice providing a first, a second and a third valve state, which in the first state connects the first orifice with the second orifice, in the second state connects the second orifice with the third orifice, and in the third state closes internal passage between all orifices, the valve system connected from the first orifice and a conduit to the pressurized source of carbon dioxide gas, and a closure assembly having an interface to a nozzle of a container for liquid and an orifice connected through a conduit to the second orifice of the three way valve system.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 21, 2004
    Inventor: Vinit Chantalat
  • Patent number: 6831891
    Abstract: A method for managing data traffic in nodes in a fabric network, each node having internally-coupled ports, follows the steps of establishing a managed queuing system comprising one or more queues associated with each port, for managing incoming data traffic; and accepting or discarding data directed to a queue according to the quantity of data in the queue relative to queue capacity. In one preferred embodiment the managed system accepts all data directed to a queue less than full, and discards all data directed to a queue that is full. In some alternative embodiments the queue manager monitors quantity of data in a queue relative to queue capacity, and begins to discard data at a predetermined rate when the quantity of queued data reaches the threshold. In other cases the queue manager increases the rate of discarding as the quantity of queued data increases above the preset threshold, discarding all data traffic when the queue is full.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: December 14, 2004
    Assignee: Pluris, Inc.
    Inventors: Deepak Mansharamani, Erol Basturk