Abstract: An ice maker comprising an elongated freezing tray (100) having arcuately shaped cross sectional configuration with equal-spaced separators (120) formed therein each in a plane normal to the axis of the elongated freezing tray (100) and comprising a rotatable assembly comprising a first hollow, cylindrical shaft (100) rotatably secured near both ends of the tray (100) substantially coincident with the axis of the tray (100) and having generally flat paddle-shaped ejector elements (114 and 115) formed thereon a second hollow, cylindrical non-rotatable shaft (160) positioned within the first cylindrical shaft (106) and non-rotatably secured at one end to the tray (100) assembly; a heating element (113) positioned within the second, hollow cylindrical shaft (160) comprising a power source (309) for supplying power thereto to heat the heating element (113) and by conduction to heat the first and second hollow, cylindrical shaft 160 and the ejector elements (114 and 115) to release the full crescent shaped ice pie

Abstract: A half crescent shaped ice piece maker comprising a freezing tray (100) having an inner surface arcuately shaped about a longitudinal radial axis and divided into crescent shaped water fillable cavities (112) in which the ice pieces are formed, and an ejector assembly (102) for rotatively moving the ice pieces out of the cavities (122) comprising a rotatable shaft (106) supported in bearings with its axis coincident with the radial axis, and with ejector assembly (102) further comprising a row of primary flexible, spring-like ejector elements (114) lying in a common plane and each secured at a first end to the shaft (106) and having its second end extend into one of the crescent shaped cavities (122) to divide the cavity (122) into rotatively leading and lagging partial crescent shaped cavities while water is injected and frozen therein and before the ejector assembly (102) is rotated to form leading and lagging rows of partial crescent ice pieces with ice bridges (152) around the edges of the ejector element

Abstract: A two level car wheel elevating device for elevating the front wheel (146) of a car having a bumper assembly (117) and comprising, first (100), second (102), third (104), and a fourth (106) top level wheel tread segments joined together to form a continuous wheel ramp surface over which the car wheel (146) can travel from ground level (142) to the fourth top level wheel tread segment (106) with a minimum of discontinuities, a pair of vertically positioned sidewalls (108, 110, and 112) positioned on either side of the wheel ramp surface and firmly secured to the wheel ramp surface to support the weight of the front or back car wheels on the wheel ramp surface, the top perimeters (136) of the sidewalls extending above the wheel ramp surface a substantially constant distance to reduce the chance of said front wheel of the car from rolling off the side of the wheel elevating device.

Abstract: An embroidering tool comprising first (18), second (23), third (25), and fourth (30) longitudinal and generally cylindrical elements coaxially arranged and each with a longitudinal bore-like cavity (22, 17, 13, and 36) extending therethrough with the first (18) and second (23) elements threadably engagable with each other with the second element (23) comprising a hypodermic type needle (10) and a threaded needle hub (16) with the hypodermic type needle (10) having its proximate end secured in the bore (17) of the needle hub and with the threaded needle hub (16) threadably engagable with a threaded first end (15) of the first element (18), and the third element (25) coaxially surrounding a portion of the first element (18) and being threaded on its inner (31) and outer (33) surfaces beginning at a tapered, compressible first end (48) thereof to allow compression of the third element (25) against the first element (18) to lock the third element (25) against the first element (18) to prevent relative movement be

Abstract: A safety package (54) for preventing accidental skin pricking by a hypodermic syringe type needle (16) having a needle hub (14) joining the needle (16) to the syringe (18) and comprising a first tubular section (12) securable at its first end to the needle hub (14). A second tubular section (54) is secured at a first end to a hinge (56) and surrounds the needle (16) in a first position (FIG. 1) with a longitudinal slot (58) formed therein and positioned to pivot about the hinge (56) and away from the needle (16) to a second position (FIG. 2) with the needle (16) passing through the longitudinal slot (58, FIG. 3) to expose the needle (16) for use and, after use of the needle, to pivot the second tubular section (54) back to its first position.

Abstract: An improved mailbox comprising a first tubular shaped compartment (18) with side walls and a flat bottom (50), a hinged front door (22) and a first pivotal flag assembly (170, FIG. 10) which is normally raised by the homeowner when he places mail in the mailbox for the postman to pick up and then lower the flag assembly, a second pivotal flag assembly (24), a first cable arrangement (40) responsive to opening of the front door to raise the second flag assembly (24) and leave it raised when the front door is closed to advise the homeowner that the postman has come, and a fastening arrangement (156 FIG. 9) for disabling the first cable arrangement by the homeowner when he is away from home, so no one will know that mail is in the mailbox. A second compartment (92) positioned below the first compartment (90) comprises a lockable rear door (112) therein. The flat bottom of the first compartment (90) is separated longitudinally along its length into first and second substantially equal sections (60 and 62 FIG.

Abstract: A decoder for decoding received pseudo random sequence (PRS) codes modulated upon a carrier signal and having an original chip rate f.sub.c, and for correcting for unknown frequency shifts in the received PRS codes. The decoder includes a local oscillator for demodulating the carrier signal and detecting the received PRS codes and a signal source for generating X correction PRS codes each having a pattern of chips similar to the chip pattern of a predetermined one of the received PRS codes and each shifted in chip rate from f.sub.c by amounts which will provide a spectrum of frequencies spanning any expected frequency shift of a received PRS code. Also provided is a correlator for correlating each of the X correction PRS codes with each received PRS code at a rate f.sub.r to determine which particular correction PRS code produces the greatest correlation signal, where f.sub.r >>f.sub.c.

Abstract: A system for digitally detecting the energy content of a received analog signal of frequency f.sub.c. The system comprises signal means for generating sampling pulses of repetition rate 4 f.sub.c, a first two level signal of frequency 2 f.sub.c, whose successive level transitions occur near successive sampling pulses, a second two level signal whose successive level transitions occur near successive level transition of a first polarity of said first two level signal, and first and second interleaved trains of clock pulses each having a repetition rate 2 f.sub.c, and with each clock pulse occurring between the level transitions of successive half cycles of said first two level signal. Also provided are signal means responsive to said sampling pulses to obtain alternate I and Q samplings of said analog signal with each sampling comprising a magnitude component and a sign component.

Abstract: An interrupt signal generating means comprising a digital-to-analog (D/A) converter and means for supplying to said D/A converter a series of binary numbers at least some of which point to service subroutines in a data processor, and when converted to dc voltages by the D/A converter have values which are equal to dc voltages originating in various peripheral devices which indicate a need for servicing by certain ones of the processor subroutines. A plurality of voltage comparators compare the dc output of the D/A converter with the condition indicating voltages generated by the peripheral devices and when equality of dc voltages occurs on the inputs of a given voltage comparator, an interrupt signal is generated and supplied to the processor which then accesses the subroutine pointed to by the corresponding binary number.

Abstract: A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data words consisting of T successive series of R data words. The system comprises N memories, each having W words locations, where W.multidot.N.gtoreq.T.multidot.R and where the N memories form a single memory matrix which is employed to process every group of received data words. Writing logic is provided for writing successively received data words of a first group of data words into the N memories in a predetermined sequence. Reading logic is provided for reading from the memories every R.sup.th data word of the first group of data words written into the to leave an available word location in each instance where a data word was read therefrom.

Abstract: A general purpose retiming circuit comprising a timing signal source for generating timing signals, a plurality of N registers arranged in a row in a given order with each register having an input terminal, an output terminal, and clock input terminal and responsive to timing signals supplied thereto to transfer the signal supplied to said input terminal means to said output terminal. There is provided a serial input terminal for supplying a serial input signal thereto. Also provided are N switches arranged in the given order and each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding register of said row of N registers, and with the first input terminal of a first of the N switches being connected to the serial input terminal and the first input terminal of each of the remainder of the N switches being connected to the output terminal of the register preceding the corresponding register in the row of registers.

Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of a selected one of the input signals and comprising first and second Exclusive OR gates each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. Further connections supply the first and second input signals to the first input terminal of the first and second Exclusive OR gates, respectively.

Abstract: A FIFO system comprising an expandable number of identical FIFO chips identically interconnected to form a ring with each FIFO chip comprising a RAM memory with inboard and outboard pointing logic which, when activated, direct the writing or readout of words into or out of successive memory locations of each RAM. Each FIFO chip further comprises border transfer logic which connects each FIFO chip with the immediately preceding FIFO chip in the ring and is responsive to the writing or reading of a word into or out of the last memory location of the preceding FIFO chip memory to activate the inboard or outboard pointing logic, respectively, of each FIFO chip, and further is responsive to the writing or reading of a word into or out of the last memory location of each FIFO chip to deactivate the inboard or outboard pointer logic, respectively, of said FIFO chip.

Abstract: An improved interrogation means in a range finding system having signal generating means for generating interrogation signals having a first encoded portion and a first basic tone portion. A transponder means responds to said interrogation signal to generate and transmit a responsive signal having a second encoded portion and a second basic tone portion phase synchronous with said first encoded and basic tone portions as received at the transponder. The interrogator means has further means for storing the phases of the first encoded and basic tone portions after transmission thereof and other means for determining the difference between the stored phase of the first encoded portion and the phase of the received second encoded portion.

Abstract: A system for correlating a sampled received analog signal against a sampled reference waveform which is approximated by three quantized levels. The three levels are organized to minimize undesirable odd harmonics with the reference and to maximize the correlator output signal-to-noise ratio. The invention comprises first and second signal summers and first, second and third registers each having M corresponding stages and logic for generating and entering into the first, second and third registers, respectively, a quantized form of the received signal, at least one two-level reference signal, and at least one two-level enable signal corresponding to the at least one two-level reference signal.

Abstract: A digitized duty cycle pulse generator capable of resolution finer than the period of the available source clock signal. The invention comprises a means for generating a clock pulse signal having a repetition of f.sub.c, counter means responsive to said clock pulse signal to cycle iteratively through a count of n, and storage means for storing a variable binary value m, where m<n and m is the length of the desired duty cycle pulse, and where m/n is the duty cycle. Also provided are logic means comprising comparator means responsive to the instantaneous count l in said counter means and the value m in said storage means when m is not an integer to produce a first logic level signal when l<m and a second logic level signal when l>m during first selected cycles of said counter means through said count of n, and to produce said first logic level signal when l<(m+1) and said second logic level signal when l>(m+1) and during second selected cycles of said counter means through said count of n.

Abstract: A system for digitally processing an analog signal, such as an audio signal, for recording and playback. The system comprises means responsive to the analog signal to produce sequences of binary 1's for those portions thereof whose amplitude exceeds a given signal level and to produce sequences of binary 0's for those portions thereof whose amplitude is less than said given signal level, and encoding means responsive to each sequence in the order of their occurrence to form a digital word representing the number of bits in each sequence. Also provided are memory means for storing said digital words in said order of occurrence, and means responsive to the stored digital words, in said order of occurrence, to produce a two level signal whose first level represents said sequences of binary 1's and whose second level represents said sequences of binary 0's. Filtering means can be provided to filter the two level signal to produce an apporoximate reproduction of the original analog signal.

Abstract: A very inexpensive computer input device for music information includes a piano-type keyboard unit adapted to be fastened on to a standard alpha-numeric computer keyboard so that manual "playing" of music on the piano keyboard results in actuation of alpha-numeric keys and the recording of the music in the computer memory, for later playback in audible form, or print-out in sheet music form.

Abstract: A digitally controlled oscillator for generating a plurality of signals spaced apart by very small frequency increments. The system comprises first means for generating a source signal of frequency f.sub.c, second means responsive to said first signal to produce a first binary output signal of frequency Nf.sub.c /2.sup.n, where n is a variable integer. Also provided are first frequency divider means responsive to said first binary output signal to produce a second binary output signal of frequency Nf.sub.c /2.sup.n+m, where m is another integer and second frequency divider means also responsive to said first signal f.sub.c to produce a third binary output signal of frequency f.sub.c /2.sup.T. Further provided are logic means responsive to said second and third binary output signals to produce a fourth binary output signal of average frequency f.sub.c /2.sup.T +Nf.sub.c /2.sup.n+m.

Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of both of said input signals and comprising first and second voltage comparators each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. First and second input signals are supplied to the first input terminals of the first and second voltage comparators, respectively. A pulse generator responds to each level transition of said first input signal to produce a clock pulse.