Abstract: In a data processor system comprising memory means containing subroutines each having low level instructions with the last instruction being an INTERPRET instruction, and high level language instructions which point to the starting addresses of said subroutines, a hardware high level language interpret capability comprising first and second program counter means which point respectively to said high level language instructions and to said subroutine instructions, and control and timing means responsive to an INTERPRET instruction to load said second program counter means with the subroutine address contained in the high level language instruction pointed to by said first program counter means. Said second program counter means is responsive to said control and timing means to execute the instructions in said subroutine.

Abstract: A television system including a transmitter and a receiver and first logic means in said transmitter for generating a composite video signal whose only synchronizing signals consist of coded signals occurring during a predetermined portion of the vertical blanking periods of said television signal. A second logic means at said receiver detects said coded signals by correlation means and then generates and substitutes for said coded signals conventional vertical and horizontal synchronizing pulses.

Abstract: A system for on-line detection of distortion in a received digital signal which is phase modulated at a data rate f.sub.d and which has a suppressed carrier frequency f.sub.c and without interrupting the signal. The system comprises means for multiplying a received digital signal by itself N times to produce a resultant signal comprising a reconstructed carrier signal of frequency Nf.sub.c and phase .phi..sub.1 and distortion produced upper and lower sidebands of frequencies f.sub.u =Nf.sub.c +f.sub.d and f.sub.l =Nf.sub.c -f.sub.d and also means for generating I and Q signals of frequency Nf.sub.c and of phase .phi..sub.1 and .phi..sub.1 .+-.90.degree., respectively. Further provided are means for generating a clock signal of frequency f.sub.d and a control means for mixing said I and Q signals with said clock signal to produce I/D and Q/D signals, respectively, where I/D represents the product of the I signal and said clock signal f.sub.

Abstract: A classifying system for determining with which group of a plurality of groups of reference file words a data word most closely compares and comprising a plurality of groups of comparison means each constructed to simultaneously and individually compare a different group of file words with said data word to produce a comparison pulse for each comparison of said data word with a file word. Means are provided for identifying each group of file words in which the comparison of not more than one file word with the data word produces a comparison pulse whose amplitude exceeds, in a given direction of polarity, the predetermined amplitude of a threshold signal, and further for identifying each of said one file words.

Abstract: A system and method for frequency division demultiplexing a received broad band signal into k.sup.m channels, each capable of containing a baseband signal component and comprising m descending tiers of identical channel division modules with the first tier thereof comprising a first module responsive to the received broad band signal to divide such broad band signal (at baseband) into k new channels each containing a baseband spectral component. Each module of each tier of modules is constructed to respond individually (by sampling and de-sampling techniques) to the spectral component in individual ones of the channels outputted from the immediately preceding higher order tier of modules to form k new additional channels each containing a baseband spectral component. Each baseband spectral component has an upper bandwidth limit which bears the same ratio to its sampling rate as the upper bandwidth limit of the originally received broad band signal bears to its sampling rate.

Abstract: In a computer system, a struture uses a method for rapidly accessing and executing a sub-routine selected in response to a service request from an external source. The system provides a storage unit containing the addresses of the sub-routines called for by the service requests, with the addresses of the sub-routine being identified by the received service requests. Also provided is a register containing the address of a given instruction and control logic responsive to a received service request to enable the register to become the main program counter and thereby point to the given instruction. The control logic responds to the given instruction to alter the contents of the register to a predetermined value. A decoder responds to the altered contents of the register to concurrently disable the main memory of the system and to enable the storage unit which then supplies the address of the selected sub-routine to the control logic while the main memory is disabled.

Abstract: A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means.

Abstract: An envelope detector with an extended linear dynamic range. A first amplitude modulated carrier signal, which can be of an intermediate frequency, is supplied to a first input terminal of a mixer, preferably balanced. The said first signal is also amplified and limited to produce a second signal which is phase synchronized with the carrier signal of said first signal, and which is supplied to the local oscillator input terminal of the mixer. The mixer responds to said first and second signals to produce a substantially dc (baseband) output signal whose waveform is similar to the envelope of said first signal.

Abstract: A data communications system for transmitting and receiving 64 different audio-frequency signals representing 64 respective alpha-numeric code symbols. A synchronizing signal consists of three time-spaced bursts where each burst consists of three audio-frequency signals. A following information signal consists of a three time-spaced message bursts where each burst consists of twenty audio-frequency signals, all three of the message bursts containing the same audio-frequency signals but in different orders. A receiver includes synchronizer means to recognize the predetermined synchronizing signal, and decoder means enabled and synchronized by the synchronizer means to decode the information signal. The audio-frequency signals may be 64 different fixed-frequency tones, or may be 64 differently-changing signals such as may be produced by unidirectional phase shift keying by 64 different pseudo-random number codes.

Abstract: A circuit for detecting each level transition of a first two-level signal of a given frequency and its leading or lagging phase relationship with a second two-level signal of said given frequency, and comprising signal level storage means having a data input terminal for receiving said first signal, a first output terminal, and a first clock pulse input terminal, and constructed to store the signal level supplied to its data input terminal and to transfer said stored signal level to its output terminal when a clock pulse is supplied to the clock pulse input terminal. First and second voltage comparator means each have a first input terminal for receiving said first and second signals, respectively, a second input terminal connected to said first output terminal and each constructed to respond to equal or non-equal signal levels supplied to their first and second input terminals to produce first and second input signals, respectively.

Abstract: A system for detecting and correcting a stuck condition on the bus lines of a parallel multi-channel data transmission system. The system comprises a transmitter for generating N data signal having first and second logic levels, a receiver for receiving said N signals, and a plurality of N data channels connecting said transmitter with said receiver. Each data channel comprises first and second Exclusive OR (XOR) gate means each having first and second input means and an output means. A data input signal is supplied to the first input means of said first XOR gate and the output of the second XOR gate is supplied to said receiver. Bus line means connects the output means of said first OR gate to the first input means of said second XOR gate.

Abstract: A demodulator for demodulating an encoded signal comprising first and second predetermined patterns of contiguous signal segments of frequencies f.sub.1 and f.sub.2. A first signal processing means comprises first correlation means including a reference signal which is correlative with the signal segments of frequency f.sub.1 of said first and second patterns to produce a first and second output signals when correlation occurs. A second signal processing means comprising second correlation means including a reference signal which is correlative with the signal segments of frequency f.sub.2 of said first and second patterns to produce third and fourth output signals when correlation occurs. The said first and third output signals are combined to produce a first resultant signal indicating correlation with said first pattern of signal segments and said second and fourth output signals are combined to produce a second resultant signal indicating correlation with said second pattern of signal segments.

Abstract: A means and method for fast determination of the frequency of an input signal comprising mean for digitizing and storing the digitized bits of the input signal in an input register of N bits at a bite rate f.sub.c. Other means generate a series of digitized reference signals whose frequencies are represented by patterns of binary 1's and 0's and spaced apart by predetermined frequency intervals. At least one digitized reference signal is clocked into a reference signal register during each time period 1/f.sub.c. The digitized reference signals are successively compared to the digitized input signals to produce output signals whose magnitudes are proportional to the degree of correlation therebetween. Further, means are provided to determine the largest output signal and the frequency of the reference signal which produced said largest output signal.

Abstract: A range finding method and system comprising an interrogator and a transponder. The interrogator generates a signal with a first portion comprising a carrier signal amplitude modulated by a first two-level iterative pseudo random sequence (PRS) whose level changes coincide with level changes of a first two-level tone of frequency f.sub.T, which phase modulates said first portion. A second portion of the signal is phase modulated by the product of the PRS and said first tone. The transponder tracks the received interrogation signal and then generates and transmits a responsive signal having first and second portions comprised of a carrier signal phase modulated by a second two-level tone phase synchronized with the received first tone. The first portion is further amplitude modulated by a second iterative PRS phase synchronized with the received PRS signal, and the second portion is further phase modulated by the second, phase synchronized PRS.

Abstract: A system for detecting magnetic field direction comprising a pair of orthogonally positioned rods each having a rectangular shaped BH curve, a switching winding, and detectors for detecting the switching of magnetic polarity of each rod to either of its remanent states. A switching current having a triangularly shaped waveform is supplied through said switching windings to drive said rods between their remanent states at times depending upon their angular relationship with the external magnetic field. Counters record the difference in time, measured from the immediately preceding zero current crossover points between the switching of each rod first to one of its remanent states and then to the other of said states. The time difference in one rod is proportional to the sine of the angle between the external field and said one rod and to the cosine of the angle between the external field and the other said other rod.

Abstract: A method and means for translating frequencies, as for example, to correct a frequency error .DELTA.f.sub.d introduced into a carrier signal of frequency f.sub.c, comprising means for dividing the resultant signal frequency (f.sub.c +.DELTA.f.sub.d) by N, resulting in a divided-down frequency (f.sub.c /N+.DELTA.f.sub.d /N), with .DELTA.f.sub.d being reduced to .DELTA.f.sub.d /N, and then heterodyning the divided-down frequency with signal of frequency (f.sub.c +f.sub.c /N) to produce a resultant signal of frequency (f.sub.c +.DELTA.f.sub.d /N), the frequency error remaining at its low, divided level .DELTA.f.sub.d /N.

Abstract: A digitized multifrequency tone generator comprising a memory having N readable word locations with each location containing an amplitude representing binary word, and with the total N binary words sequentially and collectively representing a period T.sub.o of the waveform of a multifrequency tone such as a chime with certain harmonics contained therein. Memory scanning signals of frequencies Nf.sub.o, where f.sub.o =f.sub.1, f.sub.2 . . . f.sub.n, are each employed, one at a time in a predetermined chime sequence, to repeatedly and sequentially read the N words from the memory to form a sequence of chimes each of whose fundamental tone frequencies is equal to the employed scanning frequency f.sub.o =f.sub.o1, f.sub.o2 . . . f.sub.n, with the said harmonics being reproduced at the proper frequency relative to each scanning frequency. A digital-to-analog device converts the read out binary words to form the aforementioned waveform.

Abstract: A means for reducing side lobe signals and noise signals generated in a correlator in N chip positions for correlating a received input signal with a reference signal. The coincidence and non-coincidence indicating signals of first and second halves of the chip positions of the correlator are added together separately and then subtracted one from the other, with the resulting difference signal then being rectified. Such rectified difference signal which contains the side lobe signals and the noise signals but not the desired correlator indicating signal, is subtracted from the total summed and rectified signals generated by all of the N chip positions of said correlator to produce a resultant signal with much of the side lobe signals and the noise signals cancelled out.

Abstract: One of several monolithically integrated circuits acts as a control element or sensor to supply a signal to control the power supply voltage so as to maintain a predetermined output level from the other monolithically integrated circuits. A separate output circuit converts an unstable data signal into an output signal having precisely controlled output levels.

Abstract: Apparatus and method for converting an analog input signal to a digital signal by modulating the analog signal with a periodic triangular wave-shape signal to produce intermediate digital signals and Exclusive-ORing these intermediate signals with a square wave signal having the same phase as the triangular wave-shape signal.