Abstract: This invention relates to a circuit for holding a pulse at an up level during a time interval .tau. after the input signal has been removed, and to the use of the circuit to realize a monostable multivibrator. The holding circuit features a bipolar transistor that is driven into saturation by the application of an input signal in the form of a clock pulse. The hold circuit also features a control network including a diode and a drain resistor. Upon removal of the input signal the charge stored in the base of the saturated transistor is caused by the diode to flow in a controlled manner to the drain resistor so that the transistor is cut off after a time interval .tau. closely approximating the storage time t.sub.s. Thus, the holding circuit provides a pulse of width T+.tau.. A monostable multivibrator is obtained by connecting the holding circuit to one of the two inputs of a conventional NOR circuit. The other NOR circuit input receives the input clock pulse.

Abstract: A method and apparatus for the selective deposition of metal layers on a substrate. At least one metal layer is deposited in a self-aligned manner on conductive regions on the surface of isolating or semiconductive substrates, for which purpose the conductive regions are arranged facing a metal plate having at least one layer of the metal to be deposited, and Tesla currents are generated between the metal plate and the regions to be coated. The apparatus for implementing the method includes a metal plate, a Tesla transformer which is coupled to the metal plate or to a metal grid, spaced apart from the surface of the metal plate away from the conductive regions, having closely adjacent and regularly distributed spikes pointing towards the metal. This method may be used, for example, to produce conductors on or in ceramic modules, circuit cards and semiconductor elements.

Abstract: A variable axis immersion lens electron beam projection system shifts the electron beam while eliminating rapidly changing fields, eddy currents and stray magnetic fields in the target area. The electron beam projection system includes an electron beam source and a deflection means. A variable axes immersion lens for focusing the electron beam includes an upper pole piece, and a lower pole piece having a non-zero bore section, a zero bore section and an opening therebetween for inserting the target into the lens. The variable axis immersion lens provides an axial magnetic projection field which has zero first derivative in the vicinity of the target area. A magnetic compensation yoke, positioned within the bore of the upper pole piece produces a magnetic compensation field which is proportional to the first derivative of the axial magnetic projection field.

Abstract: A magnetic field generator having a conductor winding shaped to lie over the surface of a cylinder such that four pairs of straight conductor elements lie parallel to the axis of symmetry (Z axis) of the cylinder equally spaced around its periphery. These elements are joined by 90 degree arc conductor elements. The winding is such that in the straight elements of each pair, current flow is the same direction while in adjacent peripheral elements, current flow is in opposite directions so that the magnetic field due to the current flowing through the peripheral elements is zero on the Z-axis while the current flow through the straight elements forms a quadripole magnetic field about the Z-axis. Modifications of the structure can be made to provide for six-pole, 8-pole, 12-pole, etc., structures. In each case, a single conductor formed into an appropriate sequence of meanders can be used to produce the desired structure, thereby simplifying fabrication.

Abstract: A high pressure, high etch rate single wafer plasma reactor having a fluid cooled upper electrode including a plurality of small diameter holes or passages therethrough to provide uniform reactive gas distribution over the surface of a wafer to be etched. A fluid cooled lower electrode is spaced from the upper electrode to provide an aspect ratio (wafer diameter: spacing) greater than about 25, and includes an insulating ring at its upper surface. The insulating ring protrudes above the exposed surface of the lower electrode to control the electrode spacing and to provide a plasma confinement region whereby substantially all of the RF power is dissipated by the wafer. A plurality of spaced apart, radially extending passages through the insulating ring provide a means of uniformly exhausting the reactive gas from the plasma confinement region.

Abstract: An analog circuit for implementing nonlinear operators such as an Nth-root extractor or an Nth-power operator. Two input currents yield one output current having the relationship I.sub.1 =I.sub.k.sup.-n I.sub.2.sup.n+2, where n is a positive integer and I.sub.k is a gain setting current. When n=1 the circuit functions as a square root extractor or a squaring converter. The present circuit is readily implemented with bipolar technology and offers high speed performance and temperature stability without external compensation. Typical applications of the present circuit include RMS measurement, auto-correlation, power measurement and gain compression/expansion.

Abstract: An integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region into and out of the capacitive storage region. Each memory cell also includes an offset contact region which contacts an adjacent bit line. The word lines are arranged in rows and the bit lines are arranged in columns, complementary pairs of bit lines being electrically connected to alternate ones of memory cells along each column. A bit line to diffusion capacitance couples each memory cell to the one of the pair of bit lines to which it is electrically not connected. This capacitance boosts the electrical signal written into and read out from the storage capacitor.

Abstract: An integrated circuit chip includes a tristate driver which assumes an active logical state in response to a data signal at its data input and assumes a high impedance state in response to a control signal at its control input. The integrated circuit chip also includes a control signal generating network which is connected to the tristate driver's control input for producing the control signal. The control signal generating network may be tested by connecting the control signal generating network to the data input and overriding the control input to prevent the tristate driver from assuming the high impedance state. Thus, for testing purposes, the proper response of the control signal generating circuit may be ascertained by monitoring the active state of the tristate driver.

Abstract: A micro dispense valve arrangement for accurately dispensing minute quantities of a fluid. The valve arrangement interfaces an enclosed interior region under pressure with an exterior region of less pressure through an orifice opening. The orifice wall is tapered from interior to exterior to bound a frustoconical region constricting toward the exterior to accommodate a magnetizable pellet or ball. The ball is held in its seated position against the orifice wall by permanent magnets imbedded in the wall. An AC coil surrounding the orifice opening acts when energized to cause the ball to move between its seated or closed position and a non-magnetizable screen in its open position. The frequency and duration of applied positive and negative pulses driving the coil act to control the on/off fluid flow duty cycle of the valve.

Abstract: An electrically programmable read only memory assembly having cells arranged at the intersections of bit lines (BL1) and word lines (WL1, WL2), wherein each cell is formed of a bipolar transistor provided with a base region (70) and an emitter region (71) covered with a dielectric layer (2) made of an oxide or titanate of a transition metal. The cell in this condition represents a binary 0 information bit. The application of an appropriate voltage of approximately 4 volts to the pads of this cell through its corresponding bit line (BL1) and word line (WL2) causes the dielectric layer to break down and places the bit line in ohmic contact with the emitter, which sets the cell in its second condition representing a binary "1" information bit.

Abstract: A method for selectively heating an insulating layer on a semiconductor structure by a high energy transient radiation source to a temperature sufficient to cause reflow without any significant heating of the regions adjacent to or underlying the insulating layer. In one embodiment a laser tuned to the absorption wavelength of the insulating material is scanned over the surface of the semiconductor structure. In another embodiment an insulating layer and an underlying or adjacent semiconductor layer are concurrently heated by a laser tuned to an absorption wavelength common to both in order to maintain the integrity of the interface therebetween. In a further embodiment the depth of heating in an insulating layer is controlled by selecting an appropriate dwell time for a continuous wave laser and a pulse duration for a pulsed laser.

Abstract: A digital data sense amplifier is disclosed for detecting small signal outputs from a storage media or from input sensors and comprises a differential amplifier whose outputs are coupled via two capacitors to an offset circuit which generates two offsets which in turn are fed to two comparators, one for a positive signal threshold and one for a negative signal threshold. This results in peak to peak data sensing in a noisy signal environment. An alternative embodiment differentiates an inputted analog signal and outputs a digital representation of the first derivative, or rate of change of said analog signal.

Abstract: A thin film capacitor having a dual bottom electrode is provided. The bottom electrode includes a first layer of metal and a second layer of platinum, the metal of the first layer having the characteristic of forming a stable intermetallic phase with platinum during heat treatment. The first layer metal may be selected from the group consisting of Hf, Zr and Ta. The thin film capacitor may be employed as a decoupling capacitor in VLSI devices.

Abstract: An improved MOS current mirror wherein the mirror transistors are biased to operate in the saturated region near the boundary between the linear and the saturated regions to maximize the voltage gain and the power supply rejection ratio while maintaining a high output impedance.

Abstract: A coin sorter and counter includes a plurality of spaced apart sorting plates rotatably disposed within an annular drum inclined at a fixed angle with respect to the horizontal, each sorting plate including a plurality of openings therethrough configured to ratain coins of a particular size while passing all coins of a smaller size. An automatic coin feed mechanism for supplying coins to the sorting plates is energized and deenergized responsive to the level of coins on any of the plurality of plates, and an adaptive coin ejection mechanism removes sorted coins from the respective sorting plates one-by-one whereupon they are deposited into appropriate recepticles. The sorting plates and annular drum are cooperatively configured to accurately sort bent or otherwise damaged coins one-by-one without jamming. A sensor is provided adjacent the coin ejection mechanism to generate a signal each time a coin passes therethrough, the signals being detected and a count accumulated by a central processing unit.

Abstract: A surface mounted integrated (IC) device package or carrier is disclosed suitable for accommodating large terminal count IC devices in a small space. A carrier, preferably of plastic, is disclosed having notches or castillations in its sides. A first row of leads are positioned in the periphery of the package and a second row of leads are positioned in the notches, said notches formed a predetermined distance from the periphery of the package (e.g., 0.050"). Selected leads of the second row are alternated with said first row of leads. In the preferred embodiment, the first and second leads are separated by 0.025". Also in the preferred embodiment, the first and second row of leads extend over protuberances into depressions in the bottom of the package. Each of the depressions is separated by ribs from the other depressions such that the ends of the leads are disposed in the depressions and are prevented from substantial movement, thereby preventing contact with adjacent leads.

Abstract: A method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern. In a preferred embodiment, a dielectric isolated circuit is fabricated, by such selective epitaxial growth, and a subsequent oxidation of both the mono- and polycrystalline deposits. By controlling the ratio of the deposition rates, and by controlling the oxidation step, the poly deposit is substantially fully converted to oxide, while the mono is only partly oxidized, leaving a substantially coplanar, isolated matrix of passivated monocrystalline areas in which to fabricate circuit components for interconnection.

Abstract: A method for etching tapered apertures in the insulating layer between metal layers in an integrated circuit having a multilevel interconnection system. In one embodiment a thin layer of polysilicon is formed on the interlevel oxide layer followed by deposition of a photoresist layer thereon. A pattern of apertures is formed in the resist layer which is then exposed to a selective silicon etchant to form an opening in the polysilicon layer extending to the surface of the oxide layer. The polysilicon and oxide layers are then etched with a nonselective etchant. During the oxide etch the polysilicon is etched laterally, thereby widening the apertures and producing a taper in the aperture sidewalls as the etch proceeds. The magnitude of the taper is related to the thickness of the polysilicon layer. In another embodiment wherein the oxide layer directly overlies a silicon region, the polysilicon and oxide layers are first exposed to a nonselective etchant to etch partially through the oxide layer.

Abstract: A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.

Abstract: A programmable logic device is disclosed which contains additional circuitry allowing the architecture to be programmed. Operating as an input circuit or as an output circuit, the logical function of the device is selected to operate as a buffer, latch or register. When fabricated as a portion of a programmable logic array, the architecture is modified to the desired configuration by fusible connections which conduct normal operating current until overloaded by selective programming. Thereafter, the data path through the array is programmed in a normal fashion. The programmable architecture circuitry is readily fabricated in an integrated circuit form in conjunction with a programmable logic array.