Abstract: There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.

Abstract: A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

Abstract: A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

Abstract: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

Abstract: A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

Abstract: A flow control method and system including an algorithm for deciding to transmit an arriving packet into a processing queue or to discard it, or, in the case of instructions or packets that must not be discarded, a similar method and system for deciding at a service event to transmit an instruction or packet into a processing queue or to skip the service event. The transmit probability is increased or decreased in consideration of minimum and maximum limits for each flow, aggregate limits for sets of flows, relative priority among flows, queue occupancy, and rate of change of queue occupancy. The effects include protection of flows below their minimum rates, correction of flows above their maximum rates, and, for flows between minimum and maximum rates, reduction of constituent flows of an aggregate that is above its aggregate maximum. Practice of the invention results in low queue occupancy during steady congestion.

Abstract: A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.

Abstract: A method is provided of uniquely binding, through connection, a subsystem device having restricted information space for storing code, to a system having a structure for generating and delivering a unique code to identify the system to the information storage space in the subsystem. The method comprises determining if the information storage space in the subsystem has information therein when the subsystem is connected to the system. If no information is contained in the information storage space in the subsystem, the system writes the unique code from the system to the information storage space in the subsystem. If information is in the information storage space, that information is compared with the unique code in the system, and operation of the system is allowed if, and only if, the information in the information storage space matches the unique code generated by the system. A structure for performing this method is also provided.

Abstract: A frequency hopping spread spectrum apparatus and method is disclosed which mitigates interference from adjacent frequency hopping spread spectrum devices. The apparatus and method are adapted to detect the information related to the hop sequence of an adjacent interfering network device and alter its own hop sequence based on the information relating to the interfering hop sequence.

Abstract: The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is measured per interval of time and is compared to the theoretical value based on random distribution. If the missed rate is high, then the observed effect and value of increasing cache size are deduced by observing how this increase affects the distribution of hits on all cache slots. As the number of frequently hit items in proportion to the total traffic items increases, the benefits of increasing the cache size decreases.

Abstract: According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.

Abstract: A method and systems for analyzing the quality of high-speed signals, when signals can not be over-sampled due to sampler clock rates, is disclosed. According to the method of the invention, the position of a phase rotator is moved from one end to the other and data are sampled at each position (500). Then, data are formatted (505) to obtain a global value characterizing the signal behavior. Finally, this global value is corrected (510) to remove signal transition falsely detected too early. The use of the phase rotator multiplies artificially the number of sampling positions.

Abstract: A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the generated test seeds and original test seeds defining a total test seed plurality and a subset deterministic test pattern plurality. A response suppression circuit suppresses test responses from the CUT if not generated responsive to a deterministic test seed of the deterministic test pattern plurality.

Abstract: A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

Abstract: An antenna unit is provided in a wireless communication apparatus which performs wireless communication. The antenna unit has a radio wave resonance part through which a radio wave is transmitted or received, an antenna ground part electrically connected to the radio wave resonance part, and a connection part which fixes the antenna ground part at such a position that the antenna ground part is closer to the radio wave resonance part than other ground parts of the wireless communication apparatus.

Abstract: A computer system having an opening configured to accept a device, the device assembly including at least one engagement surface. 3The computer system comprises a locking mechanism disposed in the opening to releasably latch the device assembly in the opening at a preselected position. The latching mechanism includes a hand actuated assembly movable in the opening for releasably engaging the engagement surface of the device assembly when the device assembly is located in the opening. The invention also contemplates the combination of the device assembly and the computer.

Abstract: A compact sized integrated quadband antenna for portable devices used in wireless applications is provided to provide wireless wide area network quadband coverage for world wide applications. The antenna design includes a combination of F-shaped and variations of L-shaped metal pieces. The F-shaped and variations of L-shaped metal pieces are provided on a double-sided printed circuit board. The F-shaped metal piece covers 800 MHz and 900 MHz bands. Two variations of L-shaped metal pieces are provided, whereby the two variations produce two resonants in the 1800 MHz and 1900 MHz bands. The two variations of L-shaped metal pieces are provided inside the F-shaped metal piece. The laptop display frame or the metal display supporters are used as part of the antenna, the display frame or the metal display supporters providing the ground plane to the antenna design.

Abstract: A light emitting diode projection apparatus and method is provided for irradiating a subject with ultraviolet radiation, comprising a plurality of light emitting diodes configured to emit ultraviolet radiation and arranged in a matrix, and a power modulation control unit in communication with the diodes. The power modulation control unit is configured to energize and cause the diodes to emit light and thereby irradiate the subject with ultraviolet radiation sufficient to cause material physical change in the subject.

Abstract: The present invention is related to a method and system for customizing a computer system. According to a preferred embodiment, the method includes storing customization information for the computer system in a configuration mechanism and coupling the configuration mechanism to the computer system. The customization information in the configuration mechanism is then retrieved by the computer system to customize the computer system.