Abstract: A method and system for transparently encrypting (and decrypting) sensitive data stored in a directory (or other database) is provided. Sensitive data, a password for example, may be required by a client in a distributed data processing environment. When the database entry is created, the sensitive data received from a user, or more generally, a client, may be encrypted, and saved in the directory entry in encrypted form. Encryption of sensitive data may be performed in accordance with a predetermined set of policies. When the sensitive information is needed, it may be selectively delivered in encrypted or unencrypted form based on a policy in the set. Policies may include criteria external to the database, and interfaced to the database via a policy engine.

Abstract: The present invention provides a method, apparatus, and computer program product for implementing a business systems management solution for end-to-end event management. The present invention realizes a number of business systems management functionalities, including defining event databases and means for event monitoring and correlating a customer's business functions by using an enterprise view focused on a system of applications, operating systems, connections, and physical components. Together these components make up a business system as defined by the customer. As such, a business system can cross technology platforms, physical space, and comprise multiple applications, or a business system could be limited to a single platform, location, and application.

Abstract: Mechanisms for graph manipulation of transactional performance data are provided in order to identify and emphasize root causes of electronic business system transaction processing performance problems. A system transaction monitoring system, such as IBM Tivoli Monitoring for Transaction Performance™ (ITMTP) system, is utilized to obtain transaction performance data for a system. This transaction performance data is stored in a database and is utilized to present a graph of a given transaction or transactions. Having generated a graph of the transaction, and having identified problem conditions in the processing of the transaction(s), the present invention provides mechanisms for performing graph manipulation operations to best depict the root cause of the problems.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. Also provided for are retrieving data items in a computer. A plurality of hash functions of data values in a probe key are computed. A corresponding memory location is determined for each of the plurality of hash functions. Data items in each memory location are examined to determine a match with the probe key. Responsive to a match, a payload of the matching stored data item is returned. All of the steps are performed free of conditional branch instructions.

Abstract: The present invention addresses the problem of linking cross-process and cross-thread subtransactions into a single user transaction. The mechanism of the present invention employs bytecode inserted probes to dynamically detect out of process correlating tokens in an inbound request. The bytecode inserted probes retrieve the correlating token in the inbound request. Based on the correlating token retrieved, the bytecode inserted probes are then used to dynamically determine if the inbound user request should be recorded and linked to a transaction that began in another thread or process.

Abstract: A method, apparatus, and computer instructions for presenting coverage data relating to data access occurring during execution of code. The coverage data containing data access indicators associated with memory locations is obtained. The data access indicators that have been set by a processor in the data processing system in response to access of the memory locations during execution of the code by the processor are identified to form set data access indicators. Each set instruction access indicator is associated with a portion of the memory locations allocated for the code. A presentation for coverage data is generated, wherein the set data access indicators are identified in the presentation.

Abstract: Initially the amount of data is checked to determine whether a sufficient history is present for the method. Credit card accounts are classified as new, relatively new, and old cards, i.e. opened within six months, within twelve months, and over twelve months ago. The balances for each of the three categories are calculated for each month. The average balance percentages of cards opened within six months and twelve months for the last twenty-four months is calculated and teaser surfers are defined as either having average percentages within the last twenty-four months for all credit cards opened within six and twelve months are greater than predefined percentages.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically collecting statistical information about the ability of a software application to successfully acquire a semaphore.

Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an INFINIBAND distributed system-area network that includes multiple end nodes. A manager application is established in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager application. The manager application maintains a current list of active agent applications and uses the list to manage the agent applications in the end nodes.

Abstract: A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

Abstract: A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, data gathering, and validation. In the normal mode, the instruction merely performs the function specified in the software runtime environment. An instruction in unexecuted mode, upon the next execution, is placed in data gathering mode. When an instruction in the data gathering mode is encountered, the mechanism of the present invention collects data to discover potential fixed storage access patterns. When an instruction is in validation mode, the mechanism of the present invention validates the presumed fixed storage access patterns.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol.

Abstract: A method, system, apparatus, and computer program product is presented for management of a distributed data processing system. An action at a target device is requested, and the completion of the action depends upon communication protocol operations on a set of devices along a logical route through the distributed data processing system. A set of supported protocols that are common to the set of devices along the logical route are identified, and a subset of supported protocols in the set of supported protocols that can be used to complete the action is then identified. An allowable supported protocol is selected for the action based on the type of requested action, after which the requesting application may use the action in accordance with the selected allowable supported protocol, e.g., to monitor or discover the target device. A topology mapping is used to derive an endpoint-to-endpoint route for completing the requested action.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: To reduce the total amount of reply messages in broadcasting and to make effective use of the bandwidth of a communication route without assuming an error rate in advance. Data is broadcasted to a plurality of receivers (step 11), then a maximum message length of reply messages from the receivers is calculated (step 13), and a backoff time of the reply messages is calculated (step 14). The maximum message length and the backoff time is sent to the receivers (step 15), then the reply messages having lengths of up to the specified maximum message length are generated by the receivers (step 17), and the reply messages are sent from the receivers at any time within the specified backoff time (step 19).

Abstract: An apparatus and method for scheduling data distributions to or results information from, or collectively, “jobs” to a plurality of data processing systems via a network. A connection to a target system is created. For each distribution, a session, which is an independent thread, is allocated from one of a plurality of pool of sessions and launched to effect execution of the job. Each pool corresponds to a predetermined priority level, and the session is allocated from the pool having the same priority level as the priority level of the job being scheduled. A connection supports a multiplicity of independent threads. In the event of an error, the session is released, and the scheduling of the aborted job is retried after a predetermined retry interval expires. After expiry of the retry interval, a callback method is invoked when the target system on which the scheduled job is executed becomes accessible.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: A method, system, apparatus, and computer program product is presented for management of a distributed data processing system. The network management framework is able to monitor multiple sources of network packets on various subnets within the distributed data processing system; distributed packet snoopers are deployed from a packet usage manager to monitor the multiple sources of network packets. The system administrator can request packet filtering based upon selected active users or active applications. A bandwidth history database is compiled from bandwidth usage data associated with multiple entities within the data processing system, including users, applications, and/or endpoints within the data processing system. In response to a requested action within the data processing system, bandwidth usage for the requested action can be predicted with reference to the bandwidth history database.

Abstract: A method, apparatus and computer instructions for hardware assist for autonomically patching code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.