Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shall P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A multi-channel data transfer circuit and method which provides an interface between a computer system and a multi-channel communication controller. The data transfer circuit is programmable to provide a selectable number of communication channels between the computer system and the communication controller. The data transfer circuit is further programmable to provide a selectable number of entries in each of the communication channels. In a particular embodiment, FIFO memories within the data transfer circuit are logically partitioned to provide the desired number of communication channels and the desired number of entries per channel. The data transfer circuit includes a multi-channel transmit circuit for providing data values from the computer system to the communication controller, and a multi-channel receive circuit for providing data values from the computer communication controller to the computer system.

Abstract: An output stage for a charge pump is provided that includes a first PMOS transistor, a second PMOS transistor, a pull-down transistor and a capacitor. The first PMOS transistor includes a source and a bulk region coupled to receive a charging signal, a drain coupled to a first node, and a gate coupled to receive a switching signal. The second PMOS transistor has a drain coupled to the first node, a gate coupled to receive the switching signal, and a source and a bulk region coupled to an output terminal. The capacitor is coupled between the output terminal and the ground voltage supply terminal, and charges when the first and second PMOS transistors are turned on. The pull-down transistor is configured to discharge the first node at the end of each charging cycle, thereby preventing drain-to-bulk junctions of the PMOS transistors from being forward biased during normal operation.

Abstract: A non-volatile memory (NVM) system including an array of NVM cells, a column decoder, a set of comparators and a corresponding set of NVM reference blocks is provided. During a read operation, the column decoder routes a set of read output voltages from an addressed set of the NVM cells. Each of the read output voltages is applied to a first input terminal of a corresponding comparator. Each NVM reference block generates a distinct reference voltage that is applied to a second input terminal of a corresponding comparator. Each NVM reference block is programmed to generate its distinct reference voltage in response to a random internal offset voltage in the corresponding comparator. Compensating the reference voltages in this manner enables all comparators to provide consistent results during a read operation.

Abstract: A method of operating a system-on-a-chip having a logic circuit and a thin-oxide non-volatile memory embedded or located on a single chip. In this method, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field, while the system-on-a-chip is operated in response to the data stored in the volatile memory. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the non-volatile memory cells are improved.

Abstract: A system for handling refresh of a DRAM array or other memory array requiring periodic refresh, such that the refresh does not require explicit control signaling between the memory array and a memory controller. External accesses and refresh operations are controlled so that the refresh operations do not interfere with the external accesses under any conditions. A multi-bank refresh scheme is used to reduce the number of collisions between external accesses and refresh operations. A read buffer buffers read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of the same memory bank for a long period of time. A write buffer buffers write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a single memory bank for a long period of time. Both the read and write buffers can be constructed of DRAM cells.

Abstract: A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations.

Abstract: A four-transistor RAM cell is provided by a pair of cross-coupled driver transistors configured to store a data value, and a pair of access transistors coupled to the driver transistors. The driver transistors and access transistors are sized so the driver transistors are not stronger than the access transistors. In one embodiment, the driver transistors are PMOS transistors and the access transistors are NMOS transistors, with these transistors all having substantially the same size. These PMOS and NMOS transistors are fabricated using a conventional ASIC or logic process. The PMOS transistors are located in an N-well, which is biased at a voltage greater than the VCC supply voltage. The gates of the access transistors are coupled to a word line, and the sources of the access transistors are coupled to a pair of bit lines. The bit lines are coupled a regenerative sense amplifier and a bit line equalization circuit.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. When the select signal transitions to a second state, the clock routing circuit waits for the primary clock signal to transition in a predetermined direction (i.e., rising edge or falling edge). Upon detecting the transition of the primary clock signal, the clock routing circuit holds the state of the output clock signal. The clock routing circuit then waits for the secondary clock signal to transition in the predetermined direction. Upon detecting the transition of the secondary clock signal, the clock routing circuit passes the secondary clock signal as the output clock signal.

Abstract: A non-volatile memory system having an array of 2-bit cells is provided, wherein each cell stores an odd bit and an even bit. An ERASE pulse is applied to either the odd bits or the even bits in response to an ODD_EVEN control signal, which toggles in response to an ERASE pulse. A first ERASE pulse is applied to the odd bits. An erase verify operation is then performed until failing. The erase verify operation will likely fail on an even bit, which has not yet received an ERASE pulse. After the erase verify operation fails, a second ERASE pulse is applied to the even bits in response to the toggled ODD_EVEN control signal. The erase verify operation then resumes until this operation fails, or is successfully completed. This process continues until the erase verify operation is successful. A similar method enables a plurality of NVM blocks to be erased.

Abstract: A memory array requiring periodic refresh operations is controlled such that the refresh operations do not require explicit control signaling or handshake communication between the memory array and a memory controller. External accesses and refresh operations are handled such that refresh operations do not interfere with external accesses under any conditions. A multi-bank refresh scheme reduces the number of collisions between refresh operations and external accesses. A read buffer is used to buffer read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. The memory array, read buffer and write buffer can be constructed of DRAM cells.

Abstract: The programmable interconnect points (PIPS) associated with each tile of an FPGA are programmed in response to configuration data values stored in an array of configuration memory cells. Configuration memory cells that control the configuration of the interconnect structure of the tile are located in a rectangular block within the array. For example, the configuration memory cells that control the configuration of the interconnect structure may be located in several rows of the array. This configuration enables the interconnect structure of the tile to be easily modified. To add more interconnect lines to the FPGA, the additional interconnect lines and their associated PIPs are added to the interconnect structure, and the configuration memory cells required to program the PIPs are added as additional rows in the configuration memory cell array. The pattern of configuration memory cells remains unchanged, except for the added rows of configuration memory cells.

Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.

Abstract: A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A single-port multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time.

Abstract: A method is provided to increase the speed of a non-volatile memory transistor by increasing the read channel current in the non-volatile memory transistor. This increase in speed is accomplished without increasing the VCC voltage supply source or decreasing the channel length of the non-volatile memory transistor. The increase in read channel current is accomplished by applying a low voltage to the substrate region of the non-volatile memory transistor, while grounding the source of the non-volatile memory transistor. If the non-volatile memory transistor is located in an array, the low voltage is applied to the sources and drains of non-volatile memory transistors on unselected bit lines to inhibit junction leakage channel current from these unselected non-volatile memory transistors.

Abstract: A method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to a source of a neighbor non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first and neighbor non-volatile memory transistors, (2) applying a source voltage (Vs) to a source of the first non-volatile memory transistor, (3) applying a drain voltage (Vd) to the drain of the first non-volatile memory transistor and the source of the neighbor non-volatile memory transistor, and (4) applying a forcing voltage (Vf) to a drain of the neighbor non-volatile memory transistor. In a particular embodiment, the drain voltage Vd is equal to the forcing voltage Vf. Another embodiment includes the step of applying a second forcing voltage (Vfs) to the source of another neighbor non-volatile memory transistor.

Abstract: A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: Five architectures for the implementation of virtual ground non-volatile content-addressable memory are provided. Three of the architectures are applicable to 2-bit non-volatile memory transistors having separate programming capability for two current directions (i.e., drain-to-source and source-to-drain. Another architecture is applicable to any floating gate memory transistor, including 1-bit and 2-bit non-volatile memory transistors. In general, an array of non-volatile memory transistors is arranged in a plurality of horizontal rows and vertical columns. Words are stored in selected columns of the array. Horizontal compare lines are coupled to receive a comparand word, with each compare line being coupled to the gates of the memory transistors in a row of the array. The vertically aligned source/drain regions of the memory transistors are coupled to form word lines. Sense amplifiers are coupled to selected word lines.