Abstract: A protective circuit includes a pair of diodes to protect the gate dielectric of an insulated-gate semiconductor device from over-voltage conditions, such as can occur during plasma etch manufacturing processes. The diodes are either anode- or cathode-coupled, and are connected between the gate of the device and bulk ground. Because of their opposing polarities, one of the diodes is always reverse-biased regardless of whether a positive or negative control voltage is applied to the gate of the device. As a result, the protective circuit imposes no operational restrictions on normal control voltages. At the same time, the circuit limits any plasma-induced charge buildup that can arise during manufacturing. If the gate voltage rises, a first of the two diodes is reverse biased and prevents the protective circuit from conducting. When the gate voltage reaches the reverse breakdown voltage of the first diode (plus the small forward voltage drop of the second diode), both diodes begin to conduct.

Abstract: A non-volatile memory (NVM) cell is fabricated by slightly modifying a conventional logic process. The NVM cell is fabricated by forming the gate electrode of an access transistor from a first conductive layer, and then forming a capacitor structure that contacts the gate electrode. In one embodiment, the capacitor structure is fabricated by forming a crown electrode of a capacitor structure from a second conductive layer, forming a dielectric layer over the crown electrode, and then forming an plate electrode over the dielectric layer from a third conductive layer. The crown electrode contacts the gate electrode, thereby providing an electrical connection between these electrodes. A first set of thermal cycles are performed during the formation of the capacitor structure. After the capacitor structure has been formed, P+ and/or N+ ion implantations are performed, thereby forming shallow junctions on the chip (e.g., a drain region of the access transistor).

Abstract: An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer.

Abstract: A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activated in a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A micro-sensor having have a flexible monocrystalline structure that is moved by an external force. In one embodiment, one or more pole tips are mounted on the monocrystalline structure. The monocrystalline structure is suspended over one or more planar coils such that each pole tip is suspended over a corresponding planar coil. As the monocrystalline structure moves in response to the external force, the pole tips are moved in the coils, thereby changing the inductance or inducing a voltage in the coils. In another variation, a micro-switch includes a lower structural member having a pattern of raised spacer pads that laterally surround a plurality of contact pads. The lower structural member is joined to an upper structural member that includes a frame, a platform located in the frame and a plurality of spring elements which connect the frame to the platform. The upper structural member has a conductive layer formed on its planar lower surface.

Abstract: A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By properly sizing and locating the conductive line, a desired capacitance can be coupled to the interconnect. A bias control circuit can apply or remove the bias voltage from the conductive line, thereby enabling the capacitance to be coupled or decoupled, respectively, from the interconnect. Because of its simple construction, multiple capacitive structures can be formed around a single interconnect to provide capacitive adjustment capability. By changing the number of conductive lines to which the bias voltage is applied, the total capacitance provided by the multiple capacitive structures can be varied. A feedback loop can be incorporated to provide adjustment during IC operation.

Abstract: A memory system including a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface. In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction.

Abstract: A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a word line coupling the gates of all of the memory cells in each row. Diffusion bit lines couple the first charge trapping region of each memory cell with the second charge trapping region of an adjacent memory cell. When the first charge trapping region of a memory cell is erased, the second charge trapping region of the adjacent memory cell is incidentally erased. This incidental erasure is effectively avoided by: (1) reading the bit stored in the second charge trapping region, (2) writing this bit to a storage device, (3) performing the erase operation, and then (4) restoring the bit from the storage device to the second charge trapping region of the adjacent memory cell.

Abstract: A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large non-field programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moreover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array.

Abstract: A method for stitching a plurality of mask regions including the steps of (1) defining cut regions on the mask regions, wherein the cut regions adjoin the edges of the mask regions to be stitched, (2) implementing a first set of design rules in the cut regions, and (3) implementing a second set of design rules outside of the cut regions. The mask regions can be formed on a single reticle or on a plurality of separate reticles. In one embodiment, the first set of design rules specifies that trace patterns in the cut regions have widths greater than trace patterns outside of the cut regions. In another embodiment, the first set of design rules specifies that trace patterns in the cut regions have a minimum spacing greater than trace patterns outside of the cut regions. In yet another embodiment, the first set of design rules specifies that trace patterns can be formed entirely within the cut regions.

Abstract: A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does not require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controller ensures that there will always be enough idle cycles in which the memory array can be refreshed.

Abstract: A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.

Abstract: A memory system is provided for accessing an array of polycide fuses. The memory system includes an access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuitry is provided to selectively connect one of the polycide fuses to the access control circuit in response to an address signal. In one embodiment, the access control circuit includes a partial sense amplifier circuit, which is completed by connecting one of the polycide fuses to the partial sense amplifier circuit. The completed sense amplifier circuit compares the resistance of the connected polycide fuse with a reference resistance to determine the state of the polycide fuse. The completed sense amplifier circuit provides an output signal representative of the state of the connected polycide fuse. The access control circuit also includes a programming transistor connected between an input/output supply voltage (VIO) and the partial sense amplifier circuit.

Abstract: An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles.

Abstract: An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer.

Abstract: A method of fitting a reticle pattern on a reticle, wherein the reticle pattern has dimensions that exceed the dimension of the reticle. The method includes the step of logically dividing the reticle pattern into a first window and a second window, wherein the first window and the second window overlap in a shared window region. The first and second windows are selected such that these separate windows are capable of being laid out within the dimensions of the reticle. The first window of the reticle pattern is converted from a first format, such as GDS or CIF, to a second format, such as MEBES, thereby creating a converted first window. The second window of the reticle pattern is also converted from the first format to the second format, thereby creating a converted second window. In one embodiment, resizing is performed during this conversion process. The resizing is restricted to one axis in the shared window region, thereby preventing alignment problems in a subsequent stitching process.

Abstract: A charge pump circuit having a plurality of serially-connected stages. A first stage, which operates in response to a VDD supply voltage and a clock signal, alternately charges and discharges a pair of capacitors to generate a pair of first output voltages, each having a peak voltage which is approximately twice the VDD supply voltage. The first output voltages are provided to a second stage. The second stage alternately charges and discharges a pair of capacitors using the first output voltages, thereby generating a pair of second output voltages that are approximately twice the first output voltage. Each successive charge pump stage uses the output voltages provided by the previous stage to generate output voltages that are approximately twice as large. Some voltage drop is experienced as the output voltages are transmitted from stage to stage through pass transistors. The output voltages provided by various stages can be fed back to control the charging and discharging of the capacitors within the stages.

Abstract: A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded.