Patents Represented by Attorney, Agent or Law Firm Edmund J. Walsh
  • Patent number: 5758776
    Abstract: A semiconductor chip tray holding chips in individual bins that can each be independently moved with six degrees of freedom. The bins are held in the tray with a flexural bearing system. The flexural bearing system centers the chips at a nominal position allows compliant motion of the bins. The flexural bearing system is made of four beams, with pairs joined at right angles through flexural bearings.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: June 2, 1998
    Assignee: Kinetrix, Inc.
    Inventors: Alexander H. Slocum, R. Scott Ziegenhagen, II, Richard W. Slocum, III, Luis A. Muller
  • Patent number: 5754556
    Abstract: A semiconductor memory manufacturing system including a tester sub-system and a redundancy analysis sub-system. The manufacturing system includes a transfer circuit between the test sub-system and the redundancy analysis sub-system that reduces the number of bits of data transferred to the redundancy analyzer. This speeds up the transfer process and also speeds up the redundancy analysis.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: May 19, 1998
    Assignee: Teradyne, Inc.
    Inventors: Steve G. Ramseyer, Steven A. Michaelson, Michael H. Augarten
  • Patent number: 5736850
    Abstract: A configurable probe card for use with a tester for semiconductor devices. The probe is configurable so that the contact pattern during each touch down can be different. In this way, the number of devices being tested simultaneously can be maximized. The configurable probe card increases the utilization of the tester, thereby allowing increased throughput in the semiconductor manufacturing process or, alternatively, decreasing the overall cost of testing each device.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 7, 1998
    Assignee: Teradyne, Inc.
    Inventor: Dennis Andrew Legal
  • Patent number: 5737512
    Abstract: Fast loading of a vector test pattern in a semiconductor device tester. Fast loading is achieved through the use of delta coding of vectors in conjunction with a vector cache in the vector loading circuitry of the tester. In this way, the total amount of information transmitted during the loading operation is reduced. Hardware required to implement the method is minimized by using random access memory conventionally found in automatic test equipment for the vector cache.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: April 7, 1998
    Assignee: Teradyne, Inc.
    Inventors: David M. Proudfoot, Peter A. Reichert
  • Patent number: 5730630
    Abstract: A surface mount electrical connector incorporating features to facilitate alignment of contact tails to contact pads on a printed circuit board. The contact tails are held together with a tie bar. Tabs on the tie bar are shaped to engage features on a blade of an alignment tool. The blade can be inserted into the small available on the printed circuit board, but can be easily manipulated for precise alignment of the contact tails.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: March 24, 1998
    Assignee: Teradyne, Inc.
    Inventors: Gerard C. Lacourse, Andrew K. Spence, Henry G. Vollmer
  • Patent number: 5706333
    Abstract: A cellular telephone network with the capability to detect faulty cellular telephones in use in the network. The network includes measurement units at some or all of the cell sites. The measurement units monitor the radio links between each cell site and specific cellular telephones. Measurements taken at all the cell sites are accumulated at a test system controller. The test system controller stores and processes the measurements to detect faulty cellular telephones. When a faulty cellular telephone is detected, a trouble manager notifies the subscriber of the fault so that it might be repaired before the fault affects cellular telephone service. The same measurement techniques are also used to detect fraudulent telephone usage and network problems.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: January 6, 1998
    Assignee: Teradyne, Inc.
    Inventors: James W. Grenning, Robert L. Fawley
  • Patent number: 5704793
    Abstract: A connector for printed circuit boards. Electrical connections are made between two printed boards through flex circuits which have contact pads pressed against contact pads on each of the printed circuit boards. Sufficient, uniform pressure is maintained on the contacts through the use of compressible tubes behind the contact pads on the flex circuits. The compressible tubes are spring biased towards the flex circuits. When a circuit board is engaged in the connector, it compresses the compressible tube and the spring biasing mechanism, thereby generating sufficient contact force. The connector is easy to manufacture in a variety of sizes because its pieces are modular. Many of the pieces are of uniform cross section, facilitating use of low cost extrusion operations. An embodiment is disclosed in which one printed circuit board is pivoted into contact with the contact pads.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: January 6, 1998
    Assignee: Teradyne, Inc.
    Inventors: Philip T. Stokoe, Edward C. Ekstrom
  • Patent number: 5702258
    Abstract: A modular electrical connector made from wafers. Each wafer contains one column of contact elements and is made separately. The wafers are of two different types, which snap together to form two row modules. The modules contain attachment features that allow them to be organized on a metal stiffener. Shield members can be optionally attached to each wafer so that the connector can be made in either a shielded or unshielded versions. In addition, each wafer includes windows through which selected contact elements can be cut to either improve the performance of the shields or to allow attachment of resistors.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: December 30, 1997
    Assignee: Teradyne, Inc.
    Inventors: Daniel B. Provencher, Philip T. Stokoe, Mark W. Gailus
  • Patent number: 5672064
    Abstract: A durable modular connector assembly, particularly for use as a daughter board connector. The connector is made up of connector modules organized on a stiffener. Each connector module includes an alignment block to frictionally engage contact tails. The stiffener is connected to both the base and the alignment block so that the resulting module is rigidly held together and to the stiffener. The connector is therefore less susceptible to damage.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: September 30, 1997
    Assignee: Teradyne, Inc.
    Inventors: Daniel B. Provencher, Philip T. Stokoe, David M. McNamara
  • Patent number: 5657486
    Abstract: Automatic test equipment utilizing a pipelined sequencer to retrieve test vectors from a random access memory during execution of a test pattern. The order of execution of the test vectors need not be sequential and can be dynamically altered by conditions measured during execution of a test pattern. Though pipelined, the sequencer provides one vector per cycle, even if the execution order is dynamically altered. The sequencer, because it is pipelined, can be implemented with relatively low cost, though slower speed, components. The disclosed sequencer is implemented with CMOS components.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Teradyne, Inc.
    Inventors: Allen J. Czamara, Romas P. Rudis, Ernest P. Walker
  • Patent number: 5644617
    Abstract: Apparatus and method for testing lines. The apparatus is particularly useful for testing lines in a switched network, such as might be used to electronically route telephone and computer data lines to various offices in an office building. The apparatus includes an AC test source and a DC measurement device located at a near end switch. A DC transform circuit is located at a far end switch. According to the test method, an AC test signal is injected onto a line under test at the near end. At the far end, the received signal is converted to DC, which is sent to the near end. Line attenuation, and hence fault conditions, are detected by comparing the DC signal to the transmitted AC signal. Techniques to increase the signal to noise ratio of the DC signal are also disclosed.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: July 1, 1997
    Assignee: Teradyne, Inc.
    Inventor: Kurt E. Schmidt
  • Patent number: 5621517
    Abstract: An optical fiber test unit and a method of operating it. The test unit has a laser with a computer controlled excitation current input. To take a measurement, the laser is turned on for a period of time which is approximately equal to twice the propagation time through the fiber. The laser is then turned off and the reflected signal is recorded. This signal is displayed and contains discontinuities which indicate discontinuities in the fiber. The unit provides good dynamic range, but is able to make measurements more rapidly than a conventional OTDR. It is therefore well suited for scan testing of fiber optic cable bundles.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: April 15, 1997
    Assignee: Teradyne, Inc.
    Inventors: Scott D. Jezwinski, Douglas L. Jones
  • Patent number: 5605755
    Abstract: A fiber blend for use in friction materials. The fiber contains a blend of a highly fibrillated fiber, such as a fibrillated polyacrylonitrile fiber and a fiber with a high carbon content, such as an oxidized carbon fiber precursor.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 25, 1997
    Assignee: Textron Systems Corporation
    Inventors: Arvind S. Patil, George P. Boyd, Jr.
  • Patent number: 5606262
    Abstract: A manipulator for holding and positioning a test head which is used with automatic test equipment. The manipulator includes a horizontal telescoping member attached to a vertical column. The test head is attached to an assembly suspended from this member. Six planes of free motion of the test head are provided. The column can pivot around a vertical axis. The telescoping member can move up and down along the column and can telescope in and out. The test head assembly can pivot about a vertical axis. Within the assembly, the test head can rotate around two orthogonal vertical axes. This arrangement allows the test head to be positioned into a wide variety of positions. The manipulator includes a set of cable support rings which reduces the forces a cable places on the test head when it is moved. This arrangement allows a prober to be positioned beneath the test head so that the manipulator occupies very little floor space.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 25, 1997
    Assignee: Teradyne, Inc.
    Inventors: Christopher P. Montalbano, Gregory A. Montalbano, Anthony P. Montalbano, Eric C. Fleischer
  • Patent number: 5578930
    Abstract: A manufacturing defect analyzer for printed circuit boards which can detect open circuit faults between leads of components and the printed circuit board. The manufacturing defect analyzer can operate in an inductive coupling mode or a capacitive coupling mode. The same sensors are used in each mode, allowing different leads on the same part to be tested using either technique. A method is also disclosed whereby the device is used to rapidly and accurately detect manufacturing defects.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: November 26, 1996
    Assignee: Teradyne, Inc.
    Inventor: Timothy W. Sheen
  • Patent number: 5572160
    Abstract: An RF useful for configuring RF sources and receivers to make a wide range of measurements on a device under test. The module includes a directional element which allows one receiver to measure both the input and the output signals from one test point. In addition, the module allows multiple input signals to be combined for intermodulation testing. Multiple copies of the module are used to construct multiple channels in an RF tester. At least one RF source and one RF receiver can be connected to each channel. Each lead of a device under test is assigned to a channel, but one channel may be multiplexed to more than one lead. Switching circuitry included in each module allows the source from one channel to be used as an intermodulation signal for another channel. The module includes calibration standards for source and receiver level accuracy. With this arrangement, numerous RF measurements, including measurement of s-parameters, can be made on a device under test without dedicated instruments.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: November 5, 1996
    Assignee: Teradyne, Inc.
    Inventor: Brian C. Wadell
  • Patent number: 5570383
    Abstract: Apparatus and method for detecting timing hazards which might be introduced in a pattern for execution on a tester when edges are improperly programmed in the pattern. The apparatus includes hazard detection circuits associated with the pins of the tester. Each circuit receives control inputs which specify which edges are involved in the hazard and limits on the permissible time between the specified edges. In operation, the pattern is executed repeatedly, once for each hazard which must be detected. The programmed times for the selected edge as well as the drive and format for each period of the pattern are variable inputs to the circuit.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: October 29, 1996
    Assignee: Teradyne, Inc.
    Inventors: Benjamin J. Brown, Peter A. Reichert
  • Patent number: 5566188
    Abstract: Automatic test equipment with a programmable timing generator. In the timing generator, the required delay is split into a course delay, a frequency adjustment delay, and a fine delay. The fine delays for successive cycles are temporarily stored. As the course delays pass, the fine delays are retrieved and used to generate edge signals. The frequency adjustment delay is used to offset the time at which the fine delay is retrieved by a fraction of a the resolution of the course delay. This arrangement allows the fine delay values to be retrieved at a higher rate than the rate at which the signals representing the required delays were generated. With this arrangement, the edges can be generated in a high frequency burst mode even though much of the timing generator is implemented with circuitry that has a lower operating frequency. A significant cost savings results by providing high frequency operation with less expensive components of lower operating frequency.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: October 15, 1996
    Assignee: Teradyne, Inc.
    Inventors: Bradford B. Robbins, Benjamin J. Brown, Peter A. Reichert
  • Patent number: 5554928
    Abstract: A method for detecting faults on a printed circuit board populated with semiconductor electronic components. To detect faults, signal pins on the components are taken in pairs. The an indication of the common mode resistance between those pins and ground is computed from a series of current measurements. An error is detected when the common mode resistance is outside of a predetermined range. A "learn mode" is also disclosed in which the pairs of leads used for the test are selected by taking measurements on a known good board without detailed knowledge of the semiconductor components on the board.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: September 10, 1996
    Assignee: Teradyne, Inc.
    Inventor: Philip J. Stringer
  • Patent number: 5528136
    Abstract: Automatic test equipment including a circuit to measure average current consumed by a device under test. The circuit operates during the execution of a test pattern which is not dedicated to measuring average current. The average current measuring circuit sets the measurement interval to account for a lag between the current drawn by the device under test and the current being measured.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: June 18, 1996
    Assignee: Teradyne, Inc.
    Inventors: David H. Rogoff, Edward A. Ostertag