Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Abstract: A data processing system (10) provides flexibility in interfacing with both a variety of memory devices (56, 58) and external peripheral devices (58). A control register (94) is provided for dynamically controlling a timing relationship between read and write accesses executed by the data processing system. A first set of bits (WP) stored in the control register determines an amount of time a write enable signal is asserted to indicate a length of time required to write a data value to an external device. By recognizing the difference in the timing requirements for read and write operations among different external peripheral devices and memories, as well as the difference in the timing requirements of read and write operations on the same external device, the first set of bits of the control register uses the best timing scheme available to increase the efficiency of the data processing system.

Abstract: A data processing system (20) allows a user of a pager to receive an electronic message in a language of their own choice rather than the language of a message sender. During operation, the data processing system is enabled to receive (12) an incoming message and, subsequently, detect a language of the incoming message. If the language is different than a default language of the user, the message is translated to a default language of the user (34). The message is then be displayed (40) on a screen of a paging device in the language preselected by the user or provided via a voice synthesizer (50) for an audio message. The choice of use of a visual display or use of the voice synthesizer is preselected by the user.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A method, referred to as the interactive memory mapper or IMM (322), allows a user to program a memory (9) of a data processor (14) using a computer terminal (12) as a visual interface. The IMM allows a user to view and modify a pictorial representation of a data processor's memory space. When the IMM is utilized to allow the plurality of memory blocks to be viewed on the computer terminal, each block has visible attributes corresponding to the memory located at a memory address. Each of the plurality of memory blocks may be selected using a pointing device or keyboard and the blocks' attributes may be modified via an auxiliary controls subroutine (90) of the IMM program. The selected blocks may be created, moved, and resized to either add or subtract additional memory space, but is constrained to legal configurations determined by the specification of the data processor.

Abstract: A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). The queue controller generally includes a register (52, 62) which indicates an address to be accessed and a direction control signal. Additionally, each peripheral device has a queue control register which is configured to access a selected channel of the queue memory. The queue memory system described herein also efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. For example, the queue memory system will wait (for up to thirty-two timing cycles) for a timing cycle in which the central processing unit does not require use of a bus.

Abstract: A wireless paging device (10) is able to control an electronic device (50) at a remote location. The wireless paging device includes a receiver (12) such as those typically used in pagers to detect when a particular electronic device is being remotely accessed. If the electronic device is being remotely accessed, a data processing system (20) stores an incoming message in a buffer (24) and subsequently determines if the incoming message is a command or another type of communication (34, 36). The data processing system will process a command to provide the proper control signals for controlling the functionality of the electronic device (50).

Abstract: A "vnmvh" instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing elements in the vector data processor participate in the function regardless of a setting of a status bit (Vt bit) (FIG. 6). During execution of the vnmvh instruction, the least significant bits of vector register specified in an operand are negated and moved into a plurality of history bits (Vh bits) (FIG. 6). The functionality provided by execution of vnmvh instruction allows a user to execute a nested conditional construct efficiently and effectively.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A fuzzy logic system arranges fuzzy inference rules into groups corresponding to their respective output labels. Within the fuzzy inference rules, the graded input labels are ordered in numerical order according to the grades of each input label such that all of the graded input labels utilized within any particular group of fuzzy inference rules (for each output label) is ordered in numerical order. The minimum bit state for each of the fuzzy inference rules is selected by choosing the grade within that fuzzy inference rule closest in rank to zero. The maximum bit state for each output label is selected by choosing from the minimum bit states for the various inference rules for each output label the grade farthest in rank from zero. The graded input label represented by the maximum bit state is then output as the final value for each particular output label.

Abstract: A system and method is provided for executing a low power no operation instruction in a data processor (10) with a minimal amount of power consumption. In the instruction, an opcode has a mnemonic form of "SLEEP" and an operand which specifies a number of timing cycles the instruction should be executed. During execution of the SLEEP instruction, the operand is provided to a general register (26) in a CPU (12) of the data processor (10). An ALU (28) accesses the register (26) and decrements the operand until the contents are equal to zero. When the ALU (28) has decremented the operand to zero, a next software instruction is accessed and executed by the data processor.

Abstract: An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A fuzzy inference engine (10) performs fuzzy logic operations with a high degree of accuracy in a minimal amount of time. The fuzzy inference engine (10) includes a fuzzification module (12) which decodes an input signal to access a memory location (18, 20). When accessed, the memory location provides a unary value to a rule evaluation module (26). The rule evaluation module (26) subsequently processes the unary value to indicate a relative strength of a fuzzy inference rule. Because the fuzzy logic operations use unary numbers, rather than more traditional binary numbers, the only time required to perform fuzzy logic operations is equal to only a time required for the signal to propagate through the logic gates (28, 30, 32, 34, 36, and 38) forming rule evaluation module (26).

Abstract: A pseudo-static mask option register (50) combines features of both a continuous refresh design and a static latched mask option register design. Pseudo-static mask option register (50) removes a mask option function from a main user memory (48) such that the functionality of the mask option register (50) is not limited by a plurality of electrical characteristics of the main use memory (48). When using the pseudo-static mask option register (50), a memory state of each memory bit (64, 66, 68) is read at any time. Additionally, a portion of the memory bits (64, 66, 68) is periodically refreshed such that pseudo-static mask option register (50) maintains an integrity of a value stored therein while minimizing power consumption. Pseudo-static mask option register (50) also has a non-volatile output state to allow emulation of mask options which are vulnerable to electrical disturbances.

Abstract: A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A timer (28) uses two output-compare timer channels to form a buffered pulse width modulator. A first register (62) and a second register are provided to store a first pulse width value and a second register (66), respectively. When the first register (62) is written to, a select control circuit (68) provides the first pulse width value stored therein to a channel input/output circuit (70). When the second register (66) is written to, the select control circuit (68) provides the second pulse width value stored therein to the channel input/output circuit (70). The select control circuit (68) provides one of the first and second pulse width values such that the signal output by the channel input/output circuit (70) is not erroneous. By writing a new pulse width value to a register associated with an unused channel, the pulse width modulation function is buffered.

Abstract: A low power level shift and buffer circuit (40) is used to level shift and amplify an output of an oscillator (14, 16, 18, 20, 22, 24) in a data processing application (10). A current mirror (58) and a reference current are used to provide a constant current source load for an inverter (56, 42). Separate controls for each of the two transistors forming a push/pull inverter (54, 50) eliminate a switching transient current by providing non-overlapping inputs to each of the two transistors. By eliminating the switching transient current, little power is consumed during the level shifting and amplification process. Furthermore, a significant amount of circuit area is not required and an output with fast rise and fall times is provided.

Abstract: A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.