Abstract: A transceiver (20) communicates audio and non-audio data between a variety of digital audio sources and sinks. Transceiver (20) has a receiver (34, 38) which communicates data between a modulated digital audio source (12) and an unmodulated digital audio sink (28), and a transmitter (42, 46) which communicates data between an unmodulated digital audio source (22) and a modulated digital audio sink (16). Digital data is transferred from receiver (34, 38) or received in transmitter (42, 46) in one of a plurality of eight formats. Each of the formats is designed to enable transceiver (20) to interface with a variety of digital audio sinks and sources without additional circuitry. A plurality of mode control pins determine the format provided to transceiver (20) when transmitting or receiving digital audio data.

Abstract: The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the first data processing operation, intermediate data calculations held in a plurality of temporary registers (64, 66, 68) are saved in stack memory at a location pointed to by the stack pointer register (72). The program counter is incremented to point to a second byte of the instruction. An instruction resume operation is executed and the intermediate results of the data processing operation are accessed from the stack memory and restored to respective storage locations within the data processing system. After the intermediate results are restored, the program counter is decremented to point to the first instruction byte and the instruction continues executing the data processing operation as though no interrupt occurred.

Abstract: The present invention provides a circuit (10) and method for sampling a single-ended signal and then converting the single-ended signal to a differential signal. After the single-ended signal is converted to a differential signal, then the offset voltage and low frequency noise of an operational amplifier (38) are subtracted from the differential signal using analog techniques. The subtraction operation effectively removes an operational amplifier's offset voltage and a low frequency noise from being a source of error in the differential output signal of the circuit.

Abstract: A data processor (10) increments a sixteen bit program counter value using an arithmetic logic unit, ALU, (224) and an eight bit incrementer(250). The ALU increments a low byte of the program counter value. A carry generated by incrementing the low byte is propagated to the incrementer. The incrementer then increments the high byte of the program counter value. Subsequently, the high and low bytes of the program counter value are respectively stored in a high and low program counter register (200, 206). Therefore, eight bits of an incrementer which would have typically been required to implement an incrementer for the low byte of the program counter value have been eliminated without a reduction in functionality of the data processor.

Abstract: A data processing system (10) executes a branch instruction in a straight line microcode sequence. During execution of the instruction, a control unit (56) is provided to decode the instruction to provide a plurality of control signals and to determine a data value with which to test a condition of the instruction. A constants generation circuit (222) generates a mask value in response to the plurality of control signals. An arithmetic logic unit (224) logically combines the mask value with the data value to produce a masked value. A zero detect circuit (246) subsequently tests the masked value to determine if it is equal to zero and provides a condition signal to indicate if the condition of the instruction was satisfied. If the condition of the instruction is satisfied, an offset value plus one is added to a program counter value. Otherwise, the program counter value is incremented by one.

Abstract: A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Abstract: In a fuzzy inference system comprising a plurality of fuzzy rules including input labels as antecedents, a min-max computing circuit for executing min-max computation on input label grades is disclosed. The min-max computing circuit comprises an input label sorter 10 for sorting all input label grades in their magnitude order; and min-max computing logic devices 30, 40 for executing min-max computations on the input label grades according to the grade's magnitude order.

Abstract: A lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and a feedback counter (36). The reference counter (32) and the feedback counter (36) are clocked by the reference frequency and the feedback frequency, respectively. After a first period of time, the outputs of the counters are compared. The outputs of the counters are also compared at the end of a second period of time. To be frequency locked, the two count values must be equal at both the end of the first and the second periods of time. A count window is generated from the reference frequency signal to indicate a range of frequencies for which the feedback frequency is locked. Once lock is achieved, the count window is widened such that the feedback frequency is still within a lock range when some aliasing occurs.

Abstract: A method of dual-tone multifrequency (DTMF) detection which decimates and adaptively filters an input signal is provided to efficiently detect a presence of a DTMF signal. The input signal is provided to a half-band filter (14) to be decimated in frequency in accordance with Nyquist's theory. A decimated input signal is subsequently processed to form a low frequency component signal and a high frequency component signal. The low frequency component signal is again decimated by a decimator (24). The decimated low frequency component signal and the high frequency component signal are each filtered by an adaptive fir filter (22, 26) to provide a first and a second frequency parameter and a first and a second gain factor, respectively. The first and second frequency parameters and the first and second gain factors are then tested by a tone identifier (28) to determine if the input signal includes a valid DTMF signal.

Abstract: A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

Abstract: An emulation system (10) provides a plurality of circuits (20,28) which each emulate operation of a predetermined component of a target microprocessor (24). Each of the plurality of circuits (20,28) imitates a corresponding component of the target microprocessor (24). A power supply (12) provides power to both the target microprocessor and the plurality of circuits. A first voltage value is provided to a plurality of bus drivers (22, 26, 30). A second voltage value is provided to an internal circuit of each of target microprocessor (24) and the plurality of circuits (20, 28). A current measured between the power supply and each of the circuits accurately reflects a current drawn by the circuits. By designing the target microprocessor and the plurality of circuits such that the power supplied to each is separated from the power supplied to the bus drivers of each of the devices, the operating current of the internal circuitry is accurately measured in real time.

Abstract: A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.

Abstract: A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.

Abstract: A data processing system (10) which primarily supports fractional multiplication operations has a multiplication logic circuit (20) for executing integer multiplication functions efficiently. During an integer multiplication function, two multiplicands are multiplied together as if the multiplication function was fractional. A predetermined accumulation input is stored and shifted to the right by a Right Shift Logic circuit (32) before being added to a product of the two multiplicands. An accumulated product of the multiplication function is formed by an adder (36) and shifted to the left by a Left Shift Logic circuit (38) until the accumulated product is in integer form. Implementing an integer multiplication operation with a fractional multiplier in the data processing system requires a single software instruction.

Abstract: A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.

Abstract: A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20, 44, 48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).

Abstract: A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.

Abstract: A pulse accumulator (24) operates in a pulse measurement mode. In the pulse measurement mode, accumulator (24) measured pulse lengths of consecutive high and low input signal pulses in reference to a clock signal. A leading-edge capture circuit (50) asserts a leading-edge pulse to indicate a rising edge of the input signal and a trailing-edge capture circuit (52) asserts a trailing-edge pulse to indicate a falling edge of the input signal. The leading-edge and trailing-edge pulses are logically combined (70) to provide a load signal to enable counter (76) to provide an accumulate value to a buffer register (78). After a predetermined delay (62, 64), each of the leading-edge and trailing-edge pulses are logically combined (66) to provide a clear signal which indicates the input signal has transitioned and counter (76) should be cleared to begin measuring a length of a next pulse.

Abstract: A data processing system (10) has a control selector (30) which has at least one conductor used for the common functions of shifting data and controling the generation of constants in an execution unit (26). A logic circuit (34) provides control signals to enable the control selector (30) to perform an information transfer, a shift operation, or a constant generation function. A plurality of constant signals enables a plurality of transistors (82, 114, 130, 84, 132, 86, 134) to generate a plurality of constant values. During an operation to shift data, a portion of the logic circuit (30) which generates a constant value is disabled by a Shift Disable signal. The conductors used to enable the control electrodes of the transistors during a constant generation function are used to shift data a predetermined number of bits when two shift signals are asserted.

Abstract: A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.