Abstract: A charge pump comprising a charge pump core including output switches. The charge pump core, in response to a drive signal, to generate a charge pump output. A limit swing generator, in response to an input signal, to generate the drive signal to control the charge pump core. The drive signal having voltage levels including a high level and a low level. The limit swing generator including at least one voltage generator to control the voltage levels of the drive signal such that the drive signal tracks a process variable of the output switches. The at least one voltage generator including at least one diode or diode connected device.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: Method and apparatus for equalizing the digital performance of multiple ADCs includes structure and/or steps for coupling at least one global line between the ADC's resistor ladders to allow current to flow therebetween to balance the reference voltages applied to the comparators of the ADCs. Preferably, the reference voltages are applied equally between the resistor ladders. Even more preferably, the ADC's comparators are located close to each other on a monolithic CMOS circuit.

Abstract: A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gear control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.

Abstract: A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.

Abstract: An apparatus is provided to calibrate a target electrical circuit. The target electrical circuit includes at least a first variable capacitor and a first resistive element. The apparatus includes a second variable capacitor proportionally matched to the first variable capacitor. The apparatus also includes a measurement branch having at least a second resistive element proportionally matched to the first resistive element, and a current generator to generate a current proportionally matched to a predicted current of the target circuit. The apparatus also includes a digital loop to generate a digital code based on at least a comparison between d first voltage signal of the measurement branch and a predetermined voltage.

Abstract: The present invention provides a circuit and method having a fast response time for generating a regulated voltage from a first voltage source. The circuit includes a driver for generating a drive signal. The driver has a clock input coupled to a clock signal. A charge pump that has a first voltage input coupled to the first voltage source. In response to the drive signal, the charge pump provides a pump voltage that is boosted from the first voltage. An amplifier has a reference input coupled to a reference voltage, a sense input coupled to a sense signal representative of the pump voltage, and an output. The amplifier is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch.

Abstract: In the present invention an ADC is calibrated using a matrix of selector elements to connect a plurality of reference voltages to a plurality of comparator circuits. Each selector element contains a switch connected to a memory cell. The switch is controlled to be on or off by the data in memory cell. When the switch is controlled to be on, a reference voltage at the input to the selector element is connected to the reference input of a comparator through the output of the selector element. A plurality of selector elements are connected to the reference input of each comparator in the ADC, and the selector element memory cells are programmed such as to allow one voltage from a range of reference voltages to be connected to each comparator. Each voltage in the range is a small voltage increment from the adjacent voltages connected to other selector elements.

Abstract: A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter (MDAC) operating in cooperation with a comparator which generates a two-bit digital output signal by comparison of an output of the MDAC against a pair of thresholds, wherein the thresholds are stretched outwardly from symmetrical thresholds centered at +/−1/4 of the comparison range.

Abstract: Method and apparatus for encoding data using check bits for additional data protection, in addition to the time-varying maximum transition run code which eliminates data patterns producing long runs of consecutive transitions. The check bits are inserted into codewords in preselected locations. The time-varying maximum transition run code does not permit more than j transitions beginning from an even-numbered sample period and does not permit more than j+l transitions beginning from an odd-numbered sample period, wherein j>1. This time-varying maximum transition run constraint is preserved even after the check bits are inserted, regardless of the bit values of the check bits.

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract: The effective resolution of a Position Error Signal (PES) in a disk drive servo is increased by synchronously dithering the analog PES while sampling it with an Analog-to-Digital Converter (ADC). For each cycle of a burst field signal on a servo sector, a DC offset is added to the analog PES before sampling. The offset is changed periodically during the sampling of the burst field signal. The set of all DC offsets used is evenly spread over a range which is substantially equal to the size of the least significant bit of the ADC multiplied by a positive integer.

Abstract: A method and apparatus to encode data is provided. The method includes the steps of: i) dividing the data into a plurality of blocks, with each block having a plurality of bits, wherein the plurality of blocks includes a first subset of blocks and a second subset of blocks; ii) encoding data in the first subset; arranging a codeword to include the encoded data of the first subset and the second subset; iii) scanning a plurality of segments in the codeword for at least one predetermined sequence; and iv) encoding a scanned segment when the predetermined sequence is found in the segment. A method and apparatus to decode data is also provided according to the present invention.

Abstract: A current mirror includes at least two pairs of metal oxide semiconductor field effect transistors (MOSFETs), preferably manufactured using complementary metal oxide semiconductor (CMOS) technology. Each MOSFET includes a gate, a source, and a drain, and each MOSFET operates according to a set of characteristic curves, wherein each curve includes a linear region and a saturation region. Each pair of MOSFETs is configured in series. A first current passes through the first pair of MOSFETs, and a second current passes through the second pair of MOSFETs. The first MOSFET of the first pair is electrically connected to the first MOSFET of the second pair, and the second MOSFET of the first pair is electrically connected to the second MOSFET of the second pair.

Abstract: A design-based tool for determining an error correction code (ECC) failure probability of an iterative decoding algorithm provides a technique for testing the effectiveness of the algorithm before the integrated circuit implementing the algorithm is built.

Abstract: A current source is provided according to the present invention. The current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source also includes M delay elements. An mth one of the M delay elements includes an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources.

Abstract: A linear voltage regulator generates a regulated output voltage from a low overhead input voltage. The voltage regulator includes a series pass device that generates the output voltage based on a control signal. A sense circuit generates a sense signal that is proportional to the output voltage. An integrator generates an integrated signal based on a difference between a first voltage reference and the sense signal. The integrated signal includes a first voltage reference component and a sense signal component. A summer generates the control signal in response to the integrated signal, a second voltage reference, and the sense signal. The first voltage reference component of the integrated signal has the opposite polarity of the second voltage reference and the sense signal component of the integrated signal is of the same polarity as the sense signal.

Abstract: In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of “bad” eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a “bad” sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

Abstract: A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter (MDAC) operating in cooperation with a comparator which generates a two-bit digital output signal by comparison of an output of the MDAC against a pair of thresholds, wherein the thresholds are stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.

Abstract: A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gain control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.