Abstract: A high speed write driver for an inductive head of a magnetic storage medium is provided which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. An input voltage control stage controls a voltage applied to the inductive head from the voltage source. A current supply to supplies current to the inductive head element, and a damping circuit in communication with the inductive head element. An overshoot suppressor circuit is provided such that the input voltage control tage is responsive to the overshoot suppressor circuit.

Abstract: Apparatus and method for correcting errors in data recovered from a magnetic medium includes detecting the data recovered from the read wave form, and performing an arithmetic operation such as division on the recovered data sequence to determine any non-zero remainder as an indication of an error event. The recovered data sequence is corrected in response to logical determination of a possible event error and position in the recovered data sequence from a collection of predetermined error and position for which the division of the corrected data sequence yields zero remainder.

Abstract: A circuit to generate a reference voltage from a power supply based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog to digital converter includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier is connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output, and a buffer provides a buffered output based on the output of the amplifier. A low pass filter provides a filtered voltage for the follower based on the buffered output, and a charge pump, connected to the buffered output, causes current to flow to the buffered output. The input impedance of the buffer as viewed from the charge bump is low for low frequencies and higher for higher frequencies, whereas the input impendence of the filter as viewed from the charge pump is low for high frequencies and higher for lower frequencies.

Abstract: In the present invention an ADC is calibrated using a matrix of selector elements to connect a plurality of reference voltages to a plurality of comparator circuits. Each selector element contains a switch connected to a memory cell. The switch is controlled to be on or off by the data in memory cell. When the switch is controlled to be on, a reference voltage at the input to the selector element is connected to the reference input of a comparator trough the output of the selector element. A plurality of selector elements are connected to the reference input of each comparator in the ADC, and the selector element memory cells are programmed such as to allow one voltage from a range of reference voltages to be connected to each comparator. Each voltage in the range is a small voltage increment from the adjacent voltages connected to other selector elements.

Abstract: A regulator circuit for providing a regulated voltage, comprises a driver for generating a drive signal, and a charge pump having a first voltage input coupled to a first voltage source, being responsive to the drive signal, to generate a pump voltage from the first voltage source. An amplifier having a reference input is coupled to a reference voltage, a sense input is coupled to a sense signal representative of the pump voltage, and an output is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch.

Abstract: A circuit to generate a reference voltage from a power supply based on a predetermined voltage level includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier, connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level, provides an output used to control the follower. A switched capacitor filter is provided in a feedback leg of the negative feedback arrangement. Switching of capacitors in the switched capacitor filter occurs to synchronism with phase signals for driving a switched capacitor analog to digital converter, such that the reference voltage is sampled during quiescent periods of the switched capacitor analog to digital converter.

Abstract: A circuit to generate a reference voltage from a power supply based on a predetermined voltage level, the reference voltage for use by a switched capacitor analog to digital converter includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier is connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output, and a current sink is connected to the output of the amplifier. A charge pump provides the current sink with a voltage higher than the power supply, and the follower is driven based on the current sink. The charge pump includes a pair of series-connected switching legs, each switching leg being connected to a biasable capacitor, and being driven in diagonally complementary operation together with biasing of the capacitor, so as to provide the voltage for the current sink.

Abstract: The present invention provides a circuit and method for generating a regulated voltage from a voltage source. The regulator circuit includes at least two boost circuits. A first boost circuit generates a first pump voltage. The first boost circuit includes a charge pump for generating the first pump voltage from a first voltage source. The charge pump includes a charge pump switch having a leakage current. A second boost circuit generates a second pump voltage. The second boost circuit includes a charge pump for generating the second pump voltage from a second voltage source. A compensation circuit coupled between the first boost circuit and the second boost circuit supplies a compensation current to the first boost circuit to compensate for energy losses caused by the first boost circuit leakage current. An amplifier includes a reference input coupled to a reference voltage, and a sense input coupled to a sense signal representative of the first pump voltage.

Abstract: In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between bits of the serial bit stream and reference bits of the pattern to be protected. An AND circuit accumulates the compare of a particular stage with the compare with the preceding stage. In the last stage the AND circuit provide an accumulated compare result of the preceding number of bit equaling in length the length of the bit pattern for which the compare is being performed.

Abstract: A complementary self-limiting transmission line driver is capable of driving an unterminated line driver with self-limiting slew rate control to minimize the effects of reflections on the transmission line and minimize the level of noise on power supply distribution paths. The complementary self-limiting driver circuit includes a driving circuit for receiving an output signal. In response to the output signal, a driving signal is provided to an output terminal connected to the unterminated transmission line. A first limiting circuit is connected to the driving means for controlling a slew rate of the driving means and for disabling the driving means when the output signal approaches within a threshold level of the second signal level. A second limiting circuit is optionally connected to the driving means for controlling the slew rate of the driving means and for disabling the driving means when the output signal approaches within a threshold level of the first signal level.

Abstract: A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.

Abstract: A linear regulator operable from a source voltage provides a regulated voltage to a load. The linear regulator includes a bipolar device connected between the source voltage and the load with an output of the bipolar device connected to output the regulated voltage, a feedback amplifier connected in negative feedback relationship between the output of the bipolar device and a reference voltage so as to provide a stabilized voltage, and a capacitor amplification circuit connected between the stabilized voltage and the output of the bipolar device. The capacitive amplification circuit includes a MOSFET n-channel device connected to a base of the bipolar device so as to stabilize current flow from the base to the output of the bipolar device. The capacitor amplification circuit includes an amplifier and a capacitor connected in feedback relationship with the output of the linear regulator, with an output of the amplifier stage providing a reference signal to the gate of the MOSFET device.

Abstract: A CMOS differential amplifier is provided comprising a current supply coupled to a first terminal of a power supply. A first CMOS transistor is provided having a first source, a first gate, and a first drain coupled to the current supply. A second CMOS transistor is also provided having a second source, a second gate, and a second drain coupled to the current supply. The first and second gates are inputs to the CMOS differential amplifier. A resistance is coupled between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor to improve common-mode and ground noise suppression.

Abstract: A analog function is constructed based on CMOS (complimentary metal-oxide semiconductor) technology. It is capable of providing an output voltage, which is proportional to the product of two input voltages. This analog function is insensitive to temperature and process variations by using a PMOS device as a load device for an NMOS analog function. The PMOS characteristics are used cancel or balance the variations in process and temperature in the other NMOS devices. To further control the function of the loading devices a loading device controller within the analog function compensates for changes in voltage level of the output signal due to variations in temperature and variations in manufacturing process within the function core circuit. The loading device controller has a loading control voltage terminal to provide the loading control voltage to provide temperature and process compensating biasing voltage for the load devices.

Abstract: A multi-stage amplifier having a plurality of switch mechanisms, one for each stage, that are individually controllable to vary the gain of the amplifier without compromising bandwidth. The amplifier may be embodied in a magnetic storage medium magnetic storage medium that includes a preamplifier in which the multi-stage amplifier is embodied.

Abstract: In the present invention a semiconductor integrated circuit is described to perform signal detection in a data communication system. The circuit is configured such that the capacitors used in high pass filter and a low pass filter are CMOS capacitors. The capacitors are formed from transistors where the gate is one terminal of the capacitor and the source and drain connected together form the second terminal of the capacitor. The source and drain that are connected together are connected to a voltage bias in the circuit which prevents the capacitors from being in a “floating” circuit configuration. The signal detection is done in one stage where a high pass filter is in the source of the input transistors and a low pass filter is in the drain of the input transistors. A comparator connects to the drain circuitry of the input transistors which supplies and offset voltage to the comparator.

Abstract: An ink jet recording apparatus capable of ejecting ink droplets in which the volume is precisely and easily controlled. The gradient of the pixel to be printed, based on a digital gradient input signal, is provided for printing high resolution gradient images using a low drive voltage in this ink jet head. More specifically, the ink jet recording apparatus of the present invention will include a diaphragm formed at one part of a wall of each independent ejection chamber, with electrodes formed opposite each diaphragm and spaced therefrom at a predetermined gap distance. Ink droplets are selectively ejected from nozzle openings in the ejection chamber by applying a voltage to generate an electrostatic force which momentarily deforms the diaphragm. Moreover, plurality of independent electrodes oppose each diaphragm and a pulse voltage is applied to a predetermined number of electrodes according to a gradient signal to eject ink droplets of a volume determined by the gradient signal.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digital-to-analog converter are coupled to supply corrected reference voltages to each track/hold circuit. Outputs of the comparators are supplied to a decoder which produces the digital output representative of the input voltage. The converter is calibrated before it is used for conversion by sensing the input offset voltages of each of the comparators and by altering the reference voltage for each comparator to produce a calibrated reference voltage for each comparator. A digital representation of the calibrated reference voltage for each comparator is stored in a look-up table for retrieval as needed to supply to a particular track/hold circuit a corresponding calibrated analog reference voltage for a particular comparator.

Abstract: Disclosed is a method for transient suppression in synchronous data protection systems which includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.