Patents Represented by Attorney Eric J. Nixon Peabody LLP Robinson
  • Patent number: 6166414
    Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: December 26, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
  • Patent number: 6159777
    Abstract: An improved method of forming a semiconductor device on a glass substrate is described. The method comprises forming a semiconductor film on a glass substrate, heating the semiconductor film by means of a heater to a predetermined temperature, exposing the semiconductor film to pulsed laser light after the semiconductor film has been heated to the predetermined temperature by the heating step. The thermal shock due to sharp temperature change is lessened by the pre-heating step.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: December 12, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Takenouchi, Atsunori Suzuki, Hideto Ohnuma, Hongyong Zhang, Shunpei Yamazaki
  • Patent number: 6160279
    Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an an 100 where lead serving as a crystallization-promoting catalyst is introduced.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: December 12, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama
  • Patent number: 6160753
    Abstract: Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: December 12, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Akinori Shibayama
  • Patent number: 6160269
    Abstract: A semiconductor device having a pixel provided in an active matrix. Each pixel includes a switching transistor and a pixel capacitor, the switching transistor having a semiconductor region of one conductivity type. An auxiliary capacitor is provided wherein the semiconductor region is one electrode of the auxiliary capacitor. An insulating film is provided over the switching transistor and the auxiliary capacitor. Over the auxiliary capacitor is disposed a transparent conductive film which is connected with the semiconductor region through a contact hole provided in the insulating film. Additionally, a gate line having a part serving as the other electrode of the auxiliary capacitor is provided.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: December 12, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Toshimitsu Konuma
  • Patent number: 6157563
    Abstract: Under application of a voltage V3 to a cell plate line PC, a voltage difference appearing on a bit line BL and an inverted bit line /BL in accordance with a polarized state of a memory cell capacitor and a line capacitance is amplified by a sense amplifier, thereby reading data. A read time for this read operation is tR, which is substantially the same as a write time tWL of L data and a write time tWH of H data. Also, the same voltage is used in a write operation and a read operation. Specifically, the operations are conducted with a write energy larger than a read energy. As a result, a read error can be avoided. Furthermore, since an energy not saturating polarization of a ferroelectric film is used in a write operation, there is no need to provide a voltage increasing circuit, and a high operation can be realized.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: December 5, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroshige Hirano, Masato Takeo
  • Patent number: 6156590
    Abstract: In producing TFT by crystallizing an amorphous silicon film by the action of nickel, the influence of nickel on the TFT produced is inhibited. A mask 104 is formed over an amorphous silicon film 102, and a nickel-containing solution is applied thereover. In that condition, nickel is kept in contact with the surface of the amorphous silicon film at the opening 103 of the mask. Then, this is heated to crystallize the amorphous silicon film. Next, a phosphorus-containing solution is applied thereto, so that phosphorus is introduced into the silicon film in the region of the opening 103. This is again heated, whereby nickel is gettered in the region into which phosphorus has been introduced. In this process, the nickel concentration in the silicon film is reduced.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: December 5, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Hideto Ohnuma
  • Patent number: 6154829
    Abstract: Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: November 28, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiteru Mino, Tadashi Okamoto, Hiroshi Kadota
  • Patent number: 6150203
    Abstract: To provide a method of improving the characteristics and reliability of thin film transistors (TFT) which have been formed with a highest process temperature of not more than 700.degree. C. Crystalline silicon films are thermally oxidized and TFT gate insulating films, for example, are formed with the oxide so obtained. At this time, the thermal oxidation is carried out at a temperature of 500-700.degree. C. in such a way that no thermal damage is done to the substrate, for example, and a reactive gas which contains thermally excited or decomposed oxygen or nitrogen oxide (NO.sub.X, where 0.5.ltoreq..times..ltoreq.2.5) is used for the oxidizing gas. The oxidation reaction may be promoted by heating in an atmosphere of oxides of nitrogen at a high pressure of 2-10 atmospheres. Deterioration due to the implantation of hot electrons, for example, can be prevented and element reliability can be increased by using the thermal oxide films obtained in this way as gate insulating films.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: November 21, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6150800
    Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: November 21, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Kinoshita, Shiro Sakiyama, Jun Kajiwara, Katsuji Satomi, Hiroo Yamamoto, Katsuhiro Ootani
  • Patent number: 6149988
    Abstract: A method for treating an object with a laser including emitting a laser beam from a laser; expanding the laser beam in a first direction; removing a portion of the laser beam though a mask, the portion including at least edges of the expanded laser beam extending in the first direction; and condensing the laser beam in a second direction orthogonal to the first direction in order to form a line-shaped laser beam on an object.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: November 21, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisato Shinohara, Akira Sugawara
  • Patent number: 6144082
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400.degree. C. and above. Heat treatment at a high temperature (400-700.degree. C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 .mu.m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: November 7, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 6144426
    Abstract: A liquid crystal projector in which light is effectively used and an excellent picture can be obtained is provided. In the liquid crystal projector, dichroic mirrors arranged at different angles are used to separate white light into beams of light of three primary colors of R, G, and B, and the respective beams of the light are incident on microlenses at different angles. The respective beams of light of the three primary colors are distributed by the microlenses to optical components corresponding to pixels, and highly collimated light beams can be obtained by the optical components. Since the highly collimated light beams are made incident on the pixels of the liquid crystal panel, the beams can be certainly made incident on desired pixels.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: November 7, 2000
    Assignees: Semiconductor Energy Laboratory, Sharp Kabushiki Kaisha
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata, Takeshi Nishi, Shunichi Naka, Shuhei Tuchimoto, Hiroshi Hamada, Yoshihiro Mizuguchi
  • Patent number: 6133075
    Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Hisashi Ohtani
  • Patent number: 6133620
    Abstract: A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection cont
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Uochi
  • Patent number: 6127279
    Abstract: In etching using an etching solution, irradiating ultraviolet light is irradiated into a resist patterned on an etching substrate or a film formed on the etching substrate and then an etching solution is applied to the etching substrate while rotating the etching substrate. Also, ozone water is applied in contact with the resist and then an etching solution is applied to the etching substrate while rotating the etching substrate. In crystallization using a metal element such as nickel for promoting crystallization of silicon, irradiating ultraviolet light is irradiated into a resist patterned on an substrate or a film formed on the substrate and then a nickel solution is applied to the substrate while rotating the substrate. Also, ozone water is applied in contact with the resist and then the nickel solution is applied to the substrate while rotating the substrate.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: October 3, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshimitsu Konuma
  • Patent number: 6127950
    Abstract: Image data is transmitted from a memory to a CPU (central processing unit). A transmission circuit of the memory receives an 8-bit source parallel signal, makes reference to transmission histories or to transmission predictions to generate a 2-bit coded parallel signal from the source parallel signal, and sends a serial signal as a result of converting the coded parallel signal, together with a flag signal indicative of the presence of an encoding. If the source parallel signal remains unchanged, the coded parallel signal is made to indicate 00 so that the bit transition probability of the serial signal is reduced. A reception circuit of the CPU receives the serial and flag signals and restores the 8-bit source parallel signal on the basis of reception histories or on the basis of reception predictions.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Yamauchi
  • Patent number: 6121652
    Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: September 19, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideomi Suzawa
  • Patent number: 6121660
    Abstract: In a bottom gate type semiconductor device made of a semiconductor layer with crystal structure, source/drain regions are constructed by a lamination layer structure including a first conductive layer (n.sup.+ layer), a second conductive layer (n.sup.- layer) having resistance higher than the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i layer). At this time, the n.sup.- layer acts as LDD region, and the i layer acts as an offset region is a film thickness direction.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: September 19, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Takeshi Fukunaga
  • Patent number: 6121826
    Abstract: A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: September 19, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shiro Dosho, Naoshi Yanagisawa, Masayuki Ozasa, Hidehiko Kurimoto, Tatsuo Okamoto