Patents Represented by Attorney Eric J. Nixon Peabody LLP Robinson
  • Patent number: 6121076
    Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting catalyst is introduced.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: September 19, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura
  • Patent number: 6118688
    Abstract: A ferroelectric memory device having a memory cell internally provided with first and second ferroelectric capacitors, with first and second memory cell transistors interposed between first and second bit lines (BL, /BL) and the data accumulation nodes (SN, /SN) of the first and second ferroelectric capacitors, respectively, and with a cell plate line (CP) connected to the cell plate of each of the first and second ferroelectric capacitors is controlled by the following procedures. After L data is written in the memory cell capacitor during the period between times t12 and t13, H data is written in the memory cell capacitor by control operation during the period between the time t13 and a time t14. At the time t14, the voltage on a word line (WL) is switched to L to turn OFF the first memory cell transistor, while the writing of H data in the first ferroelectric capacitor is continued by using residual charge.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: September 12, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroshige Hirano, Koji Asari
  • Patent number: 6117700
    Abstract: First, n-type contact layer of GaN, n-type cladding layer of AlGaN, active layer of InGaN, first Mg-doped layer of AlGaN and second Mg-doped layer of GaN are grown in this order over a sapphire substrate. Thereafter, the substrate, including the second Mg-doped layer, is exposed to nitrogen plasma for about 40 minutes. As a result, Mg, which has been introduced into the first and second Mg-doped layers, is activated as an acceptor. Thus, p-type cladding layer and p-type contact layer with low resistance and excellent crystallinity can be formed out of the first and second Mg-doped layers, respectively.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: September 12, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Kenji Orita, Masahiro Ishida, Shinji Nakamura, Masaaki Yuri
  • Patent number: 6115090
    Abstract: There is disclosed a structure for radiating heat generated by TFTs in a liquid crystal panel. A DLC film 125 is provided on a resin interlayer film 123 disposed on the TFTs 105, 109, and 113. The DLC film 125 can be easily formed on the resin film, and has high heat conductivity, so that the film can be made to function as a heat radiating layer.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: September 5, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6110542
    Abstract: A method for forming a film by a plasma CVD process in which a high density plasma is generated in the presence of a magnetic field is described, characterized by that the electric power for generating the plasma has a pulsed waveform. The electric power typically is supplied by microwave, and the pulsed wave may be a complex wave having a two-step peak, or may be a complex wave obtained by complexing a pulsed wave with a stationary continuous wave of an electromagnetic wave having the same or different wavelength as that of the pulsed wave. The process enables deposition of a uniform film having an excellent adhesion to the substrate, at a reduced power consumption.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: August 29, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Tohru Inoue, Shunpei Yamazaki
  • Patent number: 6107639
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6104051
    Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: August 15, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideomi Suzawa
  • Patent number: 6099390
    Abstract: A polishing pad used for polishing a film on a semiconductor wafer and made of a plastic includes a polishing pad body, and a large number of convex portions, which are provided on the surface of the polishing pad body just like so many islands and each have a flat top surface. An average length L of respective sides or diameters of the convex portions on the top surface thereof is in the range from 0.1 mm to 5.0 mm, both inclusive; an average height H of the convex portions is in the range from 0.1 mm to 0.5 mm, both inclusive; and H.ltoreq.L.ltoreq.2S is met, where S is an average space between the convex portions.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: August 8, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Mikio Nishio, Tomoyasu Murakami
  • Patent number: 6096581
    Abstract: A method for operating an active matrix display device having an active matrix circuit, a column driver circuit and a scan driver circuit including driving the active matrix circuit by the column driver circuit and the scan driver circuit, wherein each of the active matrix circuit, column driver circuit and scan driver circuit includes by thin film transistors and wherein a variation in threshold voltages of the thin film transistors of the column driver circuit is not greater than 0.05 V.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: August 1, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Patent number: 6094078
    Abstract: A PLL circuit taking a shorter time to accomplish phase locking with reduced jitter is provided. A phase/frequency detector circuit section includes: a first phase/frequency detector having phase/frequency difference detection characteristic substantially free from a dead zone; and a second phase/frequency detector having phase/frequency difference detection characteristic with a dead zone of a predetermined width. If the phase/frequency difference between a reference signal and a signal to be compared is too small to be detected by the second phase/frequency detector, only the first phase/frequency detector detects the phase/frequency difference. On the other hand, if the phase/frequency difference between the reference signal and the signal to be compared is sufficiently large, then both the first and second phase/frequency detectors detect phase/frequency difference.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: July 25, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Ryouichi Suzuki
  • Patent number: 6087725
    Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Yoichi Sasai, Satoshi Kamiyama, Tohru Saitoh, Takashi Nishikawa, Ryoko Miyanaga
  • Patent number: 6087679
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: July 11, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 6085087
    Abstract: A roaming control method for a digital mobile telephone is provided which is capable of entering a call reception state in a shortest time even if different carriers (providers) in the same frequency band are used for mobile telephone services. A roaming control method for a digital mobile telephone in a call reception control scheme at a home network and a roaming network, includes the steps of: activating a perch channel having a level of a reception radio wave larger than a predetermined level to receive broadcast information; judging whether a network number contained in the received broadcast information coincides with a home network number, and if not coincident; checking whether a roaming network number preloaded in the digital mobile telephone coincides with the network number contained in the received broadcast information, and if coincident; and receiving a call via the perch channel.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: July 4, 2000
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Hiroyuki Hori, Takashi Masuda, Gorou Serizawa
  • Patent number: 6082865
    Abstract: A projection type display device including an image pickup device is provided. A projection mirror of an OHP is made a half mirror 108, so that a picture having transmitted through the half mirror can be taken in by an image sensor 102.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: July 4, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6081978
    Abstract: A resin-encapsulated semiconductor device producing apparatus includes resin encapsulating part for encapsulating, into a unitary structure, a semiconductor-chip holding zone of a lead frame or a substrate which holds a semiconductor chip, this encapsulation being made with an encapsulating resin material. The resin encapsulating part has first and second holding members for holding the lead frame or the substrate such that the first and second holding members are opposite to each other through the lead frame or the substrate. At least one of the first and second holding members has a housing concave formed opposite to the holding zone, the housing concave being capable of housing the encapsulating resin material. A resin thickness regulating member for regulating the thickness of the encapsulating resin material is removably disposed on the bottom of the housing concave.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: July 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Masaki Utsumi, Takahiro Matsuo, Hiroshi Hidaka
  • Patent number: 6077758
    Abstract: After a pattern is transferred on silicon film crystallized by annealing, the silicon film is annealed by radiation of intense rays for a short time. Especially, in the crystallizing process by annealing, an element which promotes crystallization such as nickel is doped therein. The area not crystallized by annealing is also crystallized by radiation of intense rays and a condensed silicon film is formed.After a metal element which promotes crystallization is doped, annealing by light for a short time is performed by radiating intense rays onto the silicon film crystallized by annealing in an atmosphere containing halide. After the surface of the silicon film is oxidized by heating or by radiating intense rays in a halogenated atmosphere and an oxide film is formed on the silicon film, the oxide film is then etched. As a result, nickel in the silicon film is removed.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: June 20, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma, Yasuhiko Takemura
  • Patent number: 6075572
    Abstract: An S/N ratio is improved and flicker noises and mosquito noises are suppressed while deterioration of a resolution is suppressed. A three-dimensional cyclical digital filter (16) is interposed between a MPEG video decoder (12) and a video DAC. In accordance with a luminance input signal Yu from the MPEG video decoder (12), Yv is calculated from the following equation.Yv=Ft-K.multidot.(Ft-F(t-1))where K is a value in the range of 0.ltoreq.K<1, Ft is a present Yu input value, and F(t-1) is a one-frame preceding Yv.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: June 13, 2000
    Assignee: Kabushiki Kaisha Kenwood
    Inventor: Toru Asami
  • Patent number: 6074900
    Abstract: In producing a top gate type or a bottom gate type thin film transistor (TFT), after a metal film for forming silicide is formed on a semiconductor active layer provided on an insulating surface, an N-type or P-type impurity ion is introduced into the semiconductor active layer using an anodizable gate electrode and an anodic oxide formed on the surface of the gate electrode as masks. The exposing portion of the semiconductor active layer is reacted with the metal film, so that a silicide layer is formed in the portion. Then, non-reacted portion of the metal film is removed.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: June 13, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6072193
    Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is "gettered" into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: June 6, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 6072762
    Abstract: Between a semiconductor laser diode and an optical disk, a collimator lens for collimating a laser beam output from the semiconductor laser diode, a liquid crystal optical shutter for attenuating the collimated beam having passed through the collimator lens, and a beam splitter for splitting reflected light from the optical disk are disposed. In addition, a collective lens for collecting the collimated beam obtained by the collimator lens on a data holding surface of the optical disk is further disposed.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: June 6, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kume, Yuzaburo Ban, Isao Kidoguchi, Satoshi Kamiyama, Ayumu Tsujimura, Akihiko Ishibashi, Yoshiaki Hasegawa, Ryoko Miyanaga