Patents Represented by Attorney, Agent or Law Firm Eric J. Robinson
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Patent number: 7885612Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.Type: GrantFiled: July 23, 2008Date of Patent: February 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Takeshi Osada
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Patent number: 7823047Abstract: There is disclosed a base band signal generation device and others for processing transmission data so that a reception side can restored the data without recognizing whether the data has been subjected to a processing and transmitting the data with an appropriate efficiency corresponding to the communication quality. A transmission device T judges the communication quality of a transmission path L. When the communication quality is preferable, a four-value FSK symbol is generated from the bit of the most significant part of the encoded voice data and the bit of the least significant part. When the communication quality is not preferable, a four-value FSK symbol is generated from the bit of the most significant part of the encoded voice data and a redundant bit of “0”. However, a symbol containing a redundant bit is set to the maximum value or the minimum value of the four values which the symbol value may have.Type: GrantFiled: March 30, 2005Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha KenwoodInventor: Taichi Majima
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Patent number: 7772052Abstract: There is provided a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy. In order to solve the above problem, the manufacturing method includes a step of removing a resist mask after a step of implanting an ion of a rare gas element. Also, another manufacturing method includes a first step of implanting an ion of an impurity element for imparting a conductivity type, a second step of implanting an ion of a rare gas element, and a third step of removing a resist mask after the first step and the second step.Type: GrantFiled: November 9, 2004Date of Patent: August 10, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Shigenori Hayakawa
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Patent number: 7630883Abstract: A pitch wave signal creation method as a preliminary process for efficiently coding a speech wave signal having a fluctuated pitch period is provided. A speech signal compressing/expanding apparatus and a speech signal synthesizing apparatus using the method, and a signal processing associated therewith are further provided. The pitch wave creation method of the invention is essentially comprised of a method of detecting the instantaneous pitch period of each pitch wave element of the speech wave signal, and a process of converting a corresponding pitch wave element into a normalized pitch wave element having a predetermined fixed time length by expanding and compressing the pitch wave element on a time axis while retaining its wave pattern based on the each detected instantaneous pitch period. The speech signal having a pitch fluctuation can be compressed in high quality and high efficiency by coding or synthesizing the speech wave signal using the pitch wave signal creation method of the invention.Type: GrantFiled: August 30, 2002Date of Patent: December 8, 2009Assignee: Kabushiki Kaisha KenwoodInventor: Yasushi Sato
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Patent number: 7253437Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.Type: GrantFiled: December 22, 2004Date of Patent: August 7, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 6835986Abstract: To manufacture a liquid crystal display device with high thin film transistor accumulation, high productivity and high reliability by efficiently gettering a catalyst element, which promotes crystallization of an amorphous silicon film, from a channel region. In order to solve the above object, a step of providing a gettering sink on the outside of a p-channel thin film transistor region, and a step of removing a region provided on the outside of the thin film transistor region within the region where the catalyst element is gettered in a self-aligning manner by a source wiring or a drain wiring, are combined.Type: GrantFiled: April 2, 2001Date of Patent: December 28, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Setsuo Nakajima, Naoki Makita
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Patent number: 6836739Abstract: The spectrum of a PCM signal is divided into bands. Combinations of a reference band inclusive of a highest frequency band and another band, one of the reference band and other band being normalized, are checked to identify a combination having a highest spectrum distribution correlation. The spectrum having the same distribution as the spectrum distribution of the reference band contained in the identified combination is scaled along an envelope function and added to a higher frequency side than the reference band to generate an output signal. A presence/absence of high frequency components of a PCM signal is detected. Only if there are high frequency components, the spectrum components are added to generate an output signal.Type: GrantFiled: November 22, 2002Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha KenwoodInventor: Yasushi Sato
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Patent number: 6835523Abstract: In an apparatus for fabricating a carbon coating, an object such as a magnetic r cording medium is disposed on a side of an electrode connected to a high-frequency power supply. Ultrasonic vibrations are supplied to the object. Discharge is generated between the electrode connected to the high-frequency power supply and a grounded electrode to fabricate a carbon coating on the surface of the object. Also, an electrode interval is set to 6 mm or less, pressure between the electrodes is set to 15 Torr to 100 Torr, whereby high-density plasma is generated to form an ion sheath on an anode side. Therefore, a coating is fabricated on the surface of the object by bombardment of ions.Type: GrantFiled: September 15, 1999Date of Patent: December 28, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kenji Itoh, Shigenori Hayashi
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Patent number: 6835607Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.Type: GrantFiled: December 28, 2001Date of Patent: December 28, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiko Takemura, Satoshi Teramoto
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Patent number: 6833313Abstract: There is provided a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy. In order to solve the above problem, the manufacturing method includes a step of removing a resist mask after a step of implanting an ion of a rare gas element. Also, another manufacturing method includes a first step of implanting an ion of an impurity element for imparting a conductivity type, a second step of implanting an ion of a rare gas element, and a third step of removing a resist mask after the first step and the second step.Type: GrantFiled: April 10, 2002Date of Patent: December 21, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shigenori Hayakawa
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Patent number: 6830994Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.Type: GrantFiled: March 6, 2002Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga
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Patent number: 6828587Abstract: Crystal orientation planes exist randomly in a crystalline silicon film manufactured by a conventional method, and the orientation ratio is low with respect to a specific crystal orientation. A semiconductor film having a high orientation ratio for the {101} lattice plane is obtained if crystallization of an amorphous semiconductor film, which has silicon as its main constituent and contains from 0.1 to 10 atom % germanium, is performed after introduction of a metal element. A TFT is manufactured utilizing the semiconductor film.Type: GrantFiled: June 14, 2001Date of Patent: December 7, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
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Patent number: 6825820Abstract: A display device capable of displaying a picture of vivid colors maintaining a good balance of colors and a good balance of light-emitting brightnesses of the EL elements. The widths of the detour wirings supplying current to the power source feed lines are increased for those EL elements into which a current of a large density flows. This constitution decreases the wiring resistances of the detour wirings, decreases the potential drop through the detour wirings, and suppresses the amount of electric power consumed by the detour wirings.Type: GrantFiled: August 7, 2001Date of Patent: November 30, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Kazutaka Inukai, Mitsuaki Osame
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Patent number: 6825072Abstract: In a method of manufacturing a semiconductor device, after a lateral growth region 107 is formed by using a catalytic element for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region 108 by a heat treatment. Thereafter, a gate insulating film 113 is formed to cover active layers 110 to 112 formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.Type: GrantFiled: January 15, 2002Date of Patent: November 30, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Patent number: 6822293Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.Type: GrantFiled: January 8, 2003Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
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Patent number: 6822261Abstract: An insulated gate field effect semiconductor device comprising a substrate having provided thereon a thin-film structured insulated gate field effect semiconductor device, said device being characterized by that it comprises a metal gate electrode and at least the side thereof is coated with an oxide of the metal. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact holes for the extracting contacts of the source and drain regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate. Furthermore, the present invention provides a method for forming insulated gate field effect semiconductor devices using less masks.Type: GrantFiled: October 18, 2001Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Toshiji Hamatani
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Patent number: 6822262Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 18, 2002Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
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Patent number: 6821828Abstract: A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on a semiconductor film having a crystal structure by plasma CVD from monosilane and nitrous oxide as material gas. In a step of forming a gettering site, a semiconductor film having an amorphous structure and containing a high concentration of noble gas element, specifically, 1×1020 to 1×1021 /cm3, is formed by plasma CVD. The film is typically an amorphous silicon film. Then gettering is conducted.Type: GrantFiled: September 24, 2002Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuhiro Ichijo, Taketomi Asami, Noriyoshi Suzuki
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Patent number: 6821827Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.Type: GrantFiled: December 27, 2000Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Osamu Nakamura, Manabu Katsumura, Shunpei Yamazaki
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Patent number: 6815259Abstract: A frame-shaped holding frame which has a small thermal expansion coefficient is used. When a complex member in which a metal material is impregnated in a ceramic material, which has a smaller thermal expansion coefficient than 10 ppm/° C., is used, a warp and a wrinkle are greatly decreased. In particular, in the case of a material with a thermal expansion coefficient of 6.5 ppm/° C. or smaller, the warp and the wrinkle are not caused. When the flexible substrate is adhered to the holding frame by an adhesive, an adhesion area may be obtained so that a sufficient strength is kept. Also, since the flexible substrate is adhered onto the upper surface of the holding frame, the thickness of the holding frame is independent on fixing of the substrate. The thickness may be set so that a mechanical strength is kept and the substrate is smoothly transferred.Type: GrantFiled: August 20, 2001Date of Patent: November 9, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK CorporationInventors: Hideaki Ninomiya, Hisao Morooka, Yoshihito Yamamoto, Kazuo Nishi