Abstract: Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.

Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.

Abstract: A technique to perform error distribution in a graphics system. More particularly, embodiments of the invention include at least one technique to distribute the error resulting from converting computer generated graphics pixels from one pixel depth to another.

Abstract: A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.

Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.

Abstract: A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.

Abstract: Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Abstract: Singulating a wafer into individual die using a pre-scribing technique. Embodiments of the invention relate to scribing a wafer prior to the fabrication process in order to help preserve the integrity of the fabricated devices during singulation.

Abstract: A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.

Abstract: A method and apparatus for enabling power management of a flat-panel display is described. In one embodiment, a method involves detecting at least one display device power state and adjusting a backlight brightness in a display monitor in response to the detecting the at least one display power state. In one embodiment, a method further involves altering the brightness of a display image in order to maintain a display image quality when the backlight is adjusted.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: The present invention provides a chipset for transferring data through an electromagnetically coupled bus system. The chipset includes a modulator, a matching circuit and a demodulator. The modulator modifies a clock to encode multiple bits in a complementary pair of symbols. The matching circuit modifies the clock signal to generate a complementary pair of reference signals that is transmitted with the complementary symbol pair, and the demodulator decodes a second set of bits from selected properties of a complementary pair of transferred symbols.

Abstract: Pellicles separated by a distance sufficient to allow a purge gas help repair damage to at least one of the pellicles caused by exposure to an incident radiation and allowing at least a minimum amount of radiation to reach a semiconductor wafer sufficient to perform a desired photolythography process. Moreover, the two pellicles separated by a sufficient distance such that a dispersed purge gas dispersed between the pellicles will not absorb more than an amount of energy from the incident radiation so as to prevent a desired amount of the radiation to reach a semiconductor wafer located a certain distance away from the pellicles.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. It is a further goal of the present invention to satisfy load operations faster than prior art techniques in most cases. Finally, it is a goal of the present invention to provide an improved technique for satisfying load operations that does not significantly impact processor performance in the event that a present load is not satisfied within a predetermined amount of time.

Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

Abstract: When signaling over cables or other media having significant return impedance, it is generally more efficient to use two conductors to carry two simultaneous bi-directional signals differentially, rather than utilizing unidirectional communications. Bi-directional communications increases the aggregate bandwidth of a pair of conductors. A conversion circuit converts unidirectional signaling between an edge-based receiver and a transmitter to simultaneous differential bi-directional signaling. A receiver for receiving data includes an edge processor operative to make decisions using edges of a received data stream and a communication circuit coupled to the edge processor. The communication circuit is operative to convert communications with the edge processor from a first format, such as unidirectional signaling, to a second format, such as differential bi-directional signaling.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: A method and apparatus for resetting and modifying special registers in a security token is described. In one embodiment, a register may be reset when a reset flag is true when a special transmission on a bus demonstrates the mutual locality of the associated processor and chipset. A modify flag may also be used to indicate whether the register contents may be modified. Modifications may also be dependent upon demonstration of mutual locality.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. The present invention further relates to satisfying load operations faster than prior art techniques in most cases. Finally, the present invention provides an improved technique for satisfying load operations that does not significantly impact processor performance.

Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV×D) responsible for performing idle detection for devices. The PMV×D performs idle detection using event timers that provide an indicator as to the activity level. The PMV×D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.