Patents Represented by Attorney Eschweiler & Associates, LLC
  • Patent number: 8351537
    Abstract: Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and an interleaver depth is adjusted according to the monitored impulse noise without interrupting communication service.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Infineon Technologies AG
    Inventor: Bernd Heise
  • Patent number: 8351488
    Abstract: A receiver, includes a plurality of antennas to receive radio signals from a plurality of transmission paths, and a plurality of sets of RAKE fingers to generate first signals. Each set of RAKE fingers is coupled to a respective one of the plurality of antennas, and a weighting factor generator generates weighting factors for weighting the first signals, wherein the weighting factor for one of the first signals is generated by using first signals generated by at least two of the plurality of sets of RAKE fingers. Further, at least two of the first signals used to generate the weighting factor are received from the same transmission path.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: January 8, 2013
    Assignee: Intel Mobile Communications GmbH
    Inventors: Herbert Dawid, Juergen Niederholz, Christian Drewes, Thorsten Clevorn
  • Patent number: 8349152
    Abstract: The invention relates to a structure of a cathodic finger for diaphragm electrolysis cells consisting of an external mesh and an internal reinforcing and current-distributing structure provided with protrusions suitable for maximizing the contact points with the external mesh.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: January 8, 2013
    Assignee: Industrie de Nora S.p.A.
    Inventor: Salvatore Peragine
  • Patent number: 8351445
    Abstract: Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: January 8, 2013
    Assignee: GlobalFoundries Inc.
    Inventors: Marufa Kaniz, Jeffrey Dwork, Chin-Wei Kate Liang, Kevin Pond, legal representative, Somnath Viswanath, Robert Alan Williams
  • Patent number: 8335064
    Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Soldner, Gernot Langguth, Christian Russ, Harald Gossner
  • Patent number: 8329532
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Patent number: 8330129
    Abstract: One embodiment relates to an ion implanter. The ion implanter includes an ion source to generate an ion beam, as well as a scanner to scan the ion beam across a surface of a workpiece. The ion implanter also includes an array of absorption and radiation elements arranged to absorb energy of the scanned ion beam and radiate at least some of the absorbed energy away from the propagation direction. A detection element (e.g., an infrared detector) is arranged to detect energy (e.g., in the form of heat) radiated by the array of absorption and radiation elements and to determine a beam profile of the scanned ion beam based on the detected energy.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 11, 2012
    Assignee: Axcelis Technologies Inc.
    Inventor: William D. Lee
  • Patent number: 8331889
    Abstract: An automatic fuse architecture is described. An incoming signal is received and detected to determine whether the signal exceeds a threshold value.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: December 11, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Mikael Bergholz Knudsen, Feridoon Jalili, Michael Wilhelm, Bernd Adler
  • Patent number: 8330509
    Abstract: The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: December 11, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventor: Andreas Leistner
  • Patent number: 8325072
    Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: December 4, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventor: Franz Kuttner
  • Patent number: 8315581
    Abstract: Systems and method for implementing a transmitter with hybrid closed loop power control in a communication device.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Nick Shute, Michael Wilhelm, Andrea Camuffo, Alexander Belitzer
  • Patent number: 8315575
    Abstract: The invention relates to an integrated circuit in a mobile radio transceiver. This circuit includes a radio-frequency assembly for producing a mobile radio signal and a modulator for converting transmission data into an analogue, modulated transmission signal which is broadcast in a frequency band outside the mobile radio frequency range.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Giuseppe Li Puma, Klaus Getta
  • Patent number: 8315293
    Abstract: The invention relates to a method that includes transfer of data encoded on the basis of a first encoding scheme via an interface between a baseband assembly and a radio-frequency assembly of a mobile radio transceiver. The method further includes transfer of a data sequence which is encoded on the basis of the first encoding scheme and which identifies a change of encoding scheme from the first encoding scheme to a second encoding scheme. Lastly, the method includes transfer of data encoded on the basis of the second encoding scheme via the interface.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Dietmar Wenzel, Bernd Adler
  • Patent number: 8299771
    Abstract: In one embodiment, a circuit can selectively adjust a current for driving a load. The circuit includes a sensor configured to measure a magnetic field associated with the current and provide a sensor voltage representative thereof. A control circuit is configured to selectively adjust the current as a function of the sensor voltage and a time-varying voltage threshold. Other methods and systems are also disclosed.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 30, 2012
    Assignee: Infineon Technologies AG
    Inventors: Kyle Shawn Williams, Joseph Funyak
  • Patent number: 8289733
    Abstract: In order to convert an input power to one or more DC power levels that are provided to an output load, some aspects of the present disclosure relate to techniques for driving a switching regulator as a function of a pulsed voltage signal. In particular, this pulsed voltage signal is provided substantially at a target frequency, but exhibits frequency jitter that causes the pulsed voltage to vary slightly from the target frequency in time. The frequency jitter has a frequency range that varies as a function of the output load.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: October 16, 2012
    Assignee: Infineon Technologies AG
    Inventors: Xiaowu Gong, Siu Kam Kok, Yaw Hann Thian
  • Patent number: 8289096
    Abstract: Some aspects of the present disclosure provide for polar modulation techniques that utilize an 180° phase shift module disposed downstream of a VCO-DCO. In some embodiments, this configuration allows a polar modulator to use the VCO-DCO to achieve small phase shifts (e.g., less than or equal to) 90°, while carrying out 180° phase shifts in the 180° phase shift module downstream of the VCO-DCO.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 16, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventor: Grigory Itkin
  • Patent number: 8290094
    Abstract: Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: October 16, 2012
    Assignee: Infineon Technologies AG
    Inventors: Andreas Kolof, Dietmar König
  • Patent number: D669852
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: October 30, 2012
    Assignee: SMA Solar Technology AG
    Inventor: Harry Eppinger
  • Patent number: D671886
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 4, 2012
    Assignee: SMA Solar Technology AG
    Inventor: Lydia Schacht
  • Patent number: D672310
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 11, 2012
    Assignee: SMA Solar Technology AG
    Inventors: Peter Scharf, Gilbert Robel