Patents Represented by Attorney, Agent or Law Firm Eugene H. Valet
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Patent number: 4810544Abstract: A transparent sleeve for protecting printed media is disclosed. A sheet of transparent material with a single fold dividing said sheet into two halves has a strip of double adhesive-sided tape running the length of an edge of said sheet substantially parallel to said fold. When folded, said single sheet forms a sleeve for protecting printed media.Type: GrantFiled: December 11, 1987Date of Patent: March 7, 1989Assignee: Hewlett-Packard CompanyInventor: Mark S. Hickman
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Patent number: 4780845Abstract: A content-addressable memory cell and memory array are disclosed. Each cell comprises a random access memory storage component and a comparison component for performing the contact addressability function. In a disclosed CMOS embodiment, a DRAM cell and an exclusive-NOR gate are combined to form the CAM cell.Type: GrantFiled: July 23, 1986Date of Patent: October 25, 1988Assignee: Advanced Micro Devices, Inc.Inventor: N. Bruce Threewitt
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Patent number: 4769784Abstract: A capacitor-plate bias generator produces a voltage on the capacitor plate node which consists of a constant voltage plus the sense-level voltage. Consequently, the capacitor-plate node tracks any variations in the sense-level voltage. The constant voltage is 3V.sub.BG, or 3 times the bandgap voltage of silicon. The circuit includes a reference-voltage source which produces the sum of the sense-level voltage and V.sub.BG, and a feedback control circuit for enabling either a charge pump or a charge bleeder to regulate the capacitor-plate voltage at a level above the circuit supply voltage.Type: GrantFiled: August 19, 1986Date of Patent: September 6, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Sinan Doluca, Robert Yau
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Patent number: 4764899Abstract: A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).Type: GrantFiled: February 7, 1986Date of Patent: August 16, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Kent D. Lewallen, Steven J. Schumann
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Patent number: 4762805Abstract: An integrated circuit fabrication technique for constructing field isolation structure components and subposing electrical barrier isolation region components in a substrate is disclosed. A nitride-less mask is used to pattern a major surface of the substrate with apertures where the isolation barrier components are to be implanted. Following the formation of the isolation components, a thick oxide is formed on the substrate, masked, and etched to form field oxide structures on the major surface of the substrate. Bird beaks, bird crests, crystalline dislocations and white ribbon problems associated with nitride masking processes are virtually eliminated.Type: GrantFiled: December 17, 1985Date of Patent: August 9, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Robin W. Cheung, Hugo W. K. Chan
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Patent number: 4761154Abstract: A belt tensioner for a belt and pulley system is disclosed. The tensioner has a camming surface upon which a pulley axle rides, maintaining substantially uniform tension in the belt despite competing forces of the belt tension and a tensioner holding spring. The camming surface profile is generated, for example, when using a spring holding mechanism, by differentiating Hooke's Law.Type: GrantFiled: May 28, 1987Date of Patent: August 2, 1988Assignee: Hewlett-Packard CompanyInventors: Robert W. Beauchamp, Anthony W. Ebersole
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Patent number: 4760752Abstract: A part, providing its own plastic deformation method and an exemplary embodiment, a polycarbonate spur gear, is disclosed. In a part having at least one region adapted to be deformed due to press-fit forces acting upon said region deformation is decoupled from proximate critical surfaces by providing at least one aperture in said part in a second region which is spaced from said first region in the general direction of the resultant vector of said forces such that said deformation is relieved by said aperture.In its basic aspects, an exemplary embodiment of the present invention, a plastic spur gear which remains rotationally concentric by embodying the inventive concept is described.Type: GrantFiled: April 1, 1987Date of Patent: August 2, 1988Assignee: Hewlett-Packard CompanyInventors: Paul J. Wield, Curt N. Torgerson
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Patent number: 4742491Abstract: A single component electrically erasable memory cell is disclosed. A floating gate MOSFET having a relatively short channel is triggered into a snap-back mode positive feedback biasing mechanism. Hot-hole injection onto the floating gate during the snap-back mode neutralizes any charge stored there to represent a data bit.Type: GrantFiled: September 26, 1985Date of Patent: May 3, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Mong-Song Liang, Tien-Chiun Lee
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Patent number: 4742493Abstract: An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the secType: GrantFiled: May 19, 1986Date of Patent: May 3, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Kent D. Lewallen, Moon-Seng Kok, Steve Schumann, Woei-Jian Liu
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Patent number: 4734752Abstract: An integrated circuit device for protecting the circuitry of an integrated circuit from an electrostatic discharge into an output pin of the chip is disclosed. In a preferred embodiment, the device comprises an n-well, n-channel, polysilicon-gated FET structure, which operates in a punch-through mode, coupled to an output pad and an output buffer of the circuit. Back biasing in the chip system affords additional inhibition to turn-on during normal system operation.Type: GrantFiled: September 27, 1985Date of Patent: March 29, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Yow-Juang B. Liu, Salvatore Cagnina
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Patent number: 4733404Abstract: A transmission control circuit for use in a data terminal equipment receiver section is disclosed. The output of a phase locked loop or narrow band tuned filter input register clocking circuit which includes a quasi-differentiator and full wave rectifier is sent to a divider circuit and the divided clocking signal is then quasi-differentiated, full-wave rectified and used to drive a signal source circuit. The signal source circuit output has a polarity which is determined by the signal output of the full wave rectifier and is integrated and fed back to control inputs of the quasi-differentiators. An offset signal is also provided to the integrator. The result is an automatic adjustment of the pulse width to a fixed fraction of the input bit period.Type: GrantFiled: November 25, 1986Date of Patent: March 22, 1988Assignee: Hewlett-Packard CompanyInventor: Vladimir E. Ostoich
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Patent number: 4729061Abstract: The invention discloses an improved PC board package for at least one integrated circuit die utilizing a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat tubes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.Type: GrantFiled: May 23, 1986Date of Patent: March 1, 1988Assignee: Advanced Micro Devices, Inc.Inventor: Candice H. Brown
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Patent number: 4720687Abstract: A digital signal regenerator comprises a quantizer, a sampler, a timing extractor and a frequency and phase locked loop. The included frequency locked loop employs a frequency difference detector and a frequency generator which it shares with the included phase locked loop. The frequency difference detector includes flip-flops for generating square wave frequency difference signals, obviating the need for the multipliers, comprators and low pass filters used in prior devices. In addition, the frequency difference detector includes pulse-width modulator which is controlled by a pulse-width regulator. The regulator provides for a constant loop gain for the frequency locked loop over different reference frequencies output by the frequency generator.Type: GrantFiled: February 20, 1987Date of Patent: January 19, 1988Assignee: Hewlett-Packard CompanyInventors: Vladimir E. Ostoich, Thomas Hornak
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Patent number: 4714686Abstract: A method for forming doped, conductive plugs to fill and planarize contact windows in integrated circuits is disclosed. The process is applicable to CMOS, NMOS and bipolar technologies. Discrete, sized, contact apertures formed superposing junction regions of a substrate are filled with semiconductor material and the semiconductor material is doped to match the conductivity type of the underlying junction regions. Thus, the integrated circuit structure is substantially planarized for formation of interconnect layers.Type: GrantFiled: July 31, 1985Date of Patent: December 22, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Craig S. Sander, Balaji Swaminathan
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Patent number: 4709467Abstract: An integrated circuit fabrication technique for a maskless method of forming contact regions in integrated circuits is disclosed. By carefully controlling implant dosages, ions of one conductivity type can be introduced into substrate regions having the same conductivity type to form enhanced characteristic contact regions without affecting the operational characteristics of substrate regions having the opposite conductivity type. The resulting cross-sectional profile of the regions of the one conductivity type allows fabrication overlap tolerances to be reduced and improves the contact regions' imperviousness to the spiking phenomenon.Type: GrantFiled: March 13, 1986Date of Patent: December 1, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Yow-Juang (Bill) Liu
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Patent number: 4694205Abstract: A CMOS, midpoint sense amplification system for controlling the dynamics of the sense amplification phase of the sense cycle of a CMOS DRAM. The system includes a tracking circuit for initiating the first stage of the sense amplification phase when the differential voltage signal attains a first predetermined value. Circuitry for controlling the sense amplification rate and equalizing current supplied to the source nodes during the first stage is disclosed. In one embodiment, circuitry for detecting when the amplitude of the signal has increased to a second predetermined value and for increasing the sense amplification rate during the second and third stages of the sense amplification phase is disclosed.Type: GrantFiled: June 3, 1985Date of Patent: September 15, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Lee-Lean Shu, Tai-Ching Shyu
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Patent number: 4686559Abstract: An improved topside sealing of integrated circuit devices is disclosed which provided for hermetically sealing the top surface of the device comprising depositing a sealing layer of a nitride compound directly on the surface to be sealed. In a preferred embodiment, a protective layer may then be deposited over the nitride layer without any intervening masking steps being necessary.Type: GrantFiled: August 3, 1984Date of Patent: August 11, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Jacob D. Haskell
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Patent number: 4669179Abstract: An integrated circuit bipolar transistor fabrication technique is disclosed. The process includes steps to form shallow, self-aligned, heavily doped, extrinsic base regions which do not encroach substantially upon the emitter region. The process allows for construction of transistors which require a thinner epitaxial layer or, in the alternative, i.e., with a typical epitaxial layer, have a higher collector-to-base breakdown voltage.Type: GrantFiled: November 1, 1985Date of Patent: June 2, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Matthew Weinberg, Mammen Thomas, Shiao-Hoo Chang
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Patent number: 4665426Abstract: An erasable programmable read only memory (EPROM) integrated circuit device 2 having a topside passivation layer 9 of silicon nitride which is transparent to ultraviolet radiation is disclosed. The refractive index of the silicon nitride film is in the range of 1.93.+-.0.03.Type: GrantFiled: February 1, 1985Date of Patent: May 12, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Bert L. Allen, A. Rahim Forouhi
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Patent number: 4654824Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.Type: GrantFiled: December 18, 1984Date of Patent: March 31, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Mammen Thomas, Wen C. Ko