Abstract: A five volt only E.sup.2 PROM cell including metal bit read and bit ground column lines and polysilicon word select and program row lines. An interconnected word select and stacked gate transistor serially connect the bit read and bit ground lines. The cell also includes a tunneling structure, disposed below the program row line, for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line is disconnected from ground during the charging and uncharging operations.

Abstract: A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines in the array and dummy bit-line to a ground potential.

Abstract: A shallow capacitor cell is formed by using conventional integrated circuit processes to build a substrate mask having sublithographic dimensions. Multiple grooves, or trenches, are etched into the substrate using this mask. The capacitor dielectric layer and plate are then formed in the grooves.

Abstract: The invention discloses an improved PC board package for one or more integrated circuit dies comprising a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat pipes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.

Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.

Abstract: A low power, low output impedance, CMOS voltage reference with high source/sink current driving capability. A CMOS current mirror preamplifier includes matched transistor pairs having their W/L ratios scaled to reduce the level of current to the subthreshold region. A CMOS source follower output stage also has its transistors biased in the subthreshold region. Circuitry for protecting the preamplifier from the effects of supply voltage and output voltage bumps is also disclosed.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: In an electronic circuit having a reference voltage generator, a device is provided to stabilize the reference voltage against operating temperature variations. Temperature insensitivity is achieved by interposing a source follower type circuit, having a fuse programmable variable resistance feedback loop, between the generator and the circuitry using the reference voltage level. The present invention is particularly suitable for integrated circuits which employs a single reference potential generating circuit device.

Abstract: A temperature compensated active resistor for use on an integrated circuit semiconductor chip is formed of a N-channel MOS transistor, a string of first, second and third transistors connected as a series of diodes, and a P-channel MOS transistor. The P-channel MOS transistor has its drain electrode connected to an output terminal in which a resistance value at the output terminal remains substantially constant over a relatively wide temperature range.

Abstract: The invention comprises an improvement in the process of manufacturing an integrated circuit structure having stepped topography which comprises coating the integrated circuit structure with a polymerizable material in the substantial absence of a solvent and then polymerizing the material to provide a substantially planar surface on the integrated circuit structure.

Abstract: The ratio of silane-to-ammonia in a reaction designed to deposit a silicon nitride thin film affects the refractive index as well as the absorption coefficient of the film. By controlling the influx of these gases such that an essentially small ratio of silane-to-ammonia exists in a reaction chamber, a silicon nitride film 9 is deposited which is transparent to ultraviolet radiation 4. The exact ratio needed is dependent upon the geometry and operating parameters of the reaction chamber system employed in the deposition process. Ultraviolet light transparent silicon nitride film provides a superior passivation layer 9 for erasable programmable read only memory integrated devices 2.

Abstract: An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bonding the array of parallel conductor pins directly to an integrated circuit die while maintaining the die in a plane perpendicular to the parallel pins; and surrounding the die with a package material capable of protecting the die.

Abstract: A nonvolatile dynamic RAM capable of operating in a dynamic RAM mode and a second, nonvolatile mode, is disclosed. The nonvolatile dynamic RAM has a memory cell having a transfer transistor for coupling a storage capacitor having a floating gate to a bit line. The memory cell holds information by the storage of charge in the storage capacitor and also holds information by the storage of charge in the floating gate. This data can be stored and retrieved in a volatile mode and in a nonvolatile mode. The nonvolatile dynamic RAM has a plurality of these memory cells connected to a bit line which, in turn, is connected to a sense amplifier for determining the presence or absence of storage charges in the storage capacitor of a selected memory cell in the first mode, and for determining the presence or absence of storage charges in the floating gate of the selected memory cell in the second mode.

Abstract: A non-volatile dynamic RAM circuit where each memory cell includes an access transistor, a floating gate structure, and a recall transistor connected in series between an I/O bit line and a common line. A conducting plate and storage node of the floating gate structure functions as the volatile storage element of the cell and the floating gate functions as the non-volatile storage element.

Abstract: A semiconductor device having grooves of different depths for improved device isolation is presented. In the preferred embodiment of the present invention, a first groove and a second groove provide isolation of devices within regions of different conductivity type. The first and second grooves are each shallower than the conductivity type region in which they reside. A third groove is formed between adjacent regions of different conductivity type. The third groove is deeper than both the first groove and the second groove and extends to a depth sufficient to penetrate the substrate of the semiconductor device. The third groove operates to prevent latch-up between devices in the adjacent well regions. Filler materials are used to fill the first, second and third grooves to improve their respective isolating characteristics.

Abstract: A plurality of capacitive memory elements are coupled between two pairs of bit line and return line halves. A cross-coupled MOSFET sense amplifier, configured to operate in a race mode, connects between the two bit line/return line pairs. The return line of each bit line/return line pair is coupled to the bit line of the other pair so that when any selected memory element is read to generate a data signal on the bit line half associated with that memory element, the complement of that data signal is coupled to the other bit line half via the return line to increase the signal level differential across the sense amplifier.

Abstract: A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it are disclosed. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon having selected portions thereof reacted with a metal capable of forming a metal silicide in situ on the surface of the poly silicon strips, a further oxide layer over the metal silicide, and a metal layer providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer above the poly load resistor. This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure.

Abstract: A method is set forth for forming conductive contacts to first, second and third regions of a substrate. The substrate is covered with an insulating layer having a slot with an island therein. The island is covered with a first sacrificial layer. The substrate is covered with a conformal coating of a dielectric material. The coating is etched off with retention of sacrificial portions of the dielectric material between the island and the insulating layer. The first sacrificial layer is removed from the island while the sacrificial portions remain. A conductive layer is deposited upon the substrate. A second sacrificial layer is laid down upon the conductive layer. The second sacrificial layer is etched away along with the sacrificial portions of the dielectric material while the conductive layer is not significantly removed. Highly conductive contacts are provided with the conductive material self-aligned on the source, drain and gate.

Abstract: A fabrication method and resulting integrated circuit structure that provide a second level of interconnect, a low resistance contact strap between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings in an insulating layer on a wafer to any desired underlying circuit layers, depositing a silicide layer on the wafer, removing selected portions of the silicide layer, depositing a polysilicon layer on the wafer, lightly doping the polysilicon layer to a level appropriate for the resistor, and then removing portions of the polysilicon along with underlying silicide.