Abstract: A serial-bit digital processing system uses registers and latches to synchronize samples and justify sign-bits. Nominally each processing block in the system includes a sign extend register preceding an arithmetic element and an output register following the arithmetic element. Input registers of one arithmetic element may merge with output registers of the preceding arithmetic element. Ones of the registers include a serially coupled latch which is selectively controlled to pass serial sample bits or to replicate the sign bit. The respective registers are clocked with one of two clock signals having different numbers of pulses per sample period and the length of the respective registers are selected so that at the terminus of each sample period the bits of each sample in the processing system are appropriately justified.

Abstract: A color display system includes a cathode-ray tube and yoke. The yoke is a non-converging type. The cathode-ray tube has an electron gun for generating and directing three electron beams, a center beam and two outer beams, along paths toward a screen of the tube. The electron gun includes electrodes that comprise a beam-forming region and electrodes that form a main focusing lens. The main focusing lens is formed by at least two focusing electrodes. The focusing electrode closest to the beam-forming region includes at least two spaced parts. Each spaced part forms a portion of a dipole lens structure in the path of an outer electron beam. Means are provided for applying to at least one of the spaced parts a dynamic signal which is related to the deflection of the electron beams.

Abstract: A video display apparatus convergence and correction arrangement includes a digital signal delay circuit which uses a sample interpolation technique to provide apparent signal delays corresponding to fractional parts of whole sample periods. Adjacent digital samples are combined using fractional coefficients that sum to unity. The selection of the fractional coefficients determines the size of the smallest delay increment. The number of whole sample delay periods as well as the initial fractional coefficients for a given horizontal scan line are provided by information that is stored in a memory device during assembly or alignment of the video display apparatus.

Abstract: A phase-lock-loop circuit of a television deflection apparatus generates a first signal at the horizontal frequency and a second signal at 32 times the horizontal frequency that are both synchronized to a horizontal sync signal. A frequency divider that is outside the phase-lock-loop circuit generates from the second signal a third signal at the horizontal frequency. The frequency divider is synchronized by the first signal to cause the third signal to be in a constant phase relationship relative to that of the first signal. The third signal is used by a phase-control-loop to control the phase of the deflection current.

Abstract: A transmitter driver of this invention is applied to a programmable remote control transmitter for receiving remote control codes for remote-controlling various electric devices in the learning mode and for remote-controlling the electric devices according to the received remote control codes in the remote control mode. The transmitter driver has an output transistor for driving a transmitter constituting a part of a load upon reception of electrical pulses representing the remote control codes, a resistor device arranged between the output side of the output transistor and a given reference potential, and a control transistor device, output electrodes of which are arranged between one end of the resistor device at the side of the output transistor and the reference potential. An input terminal of the control transistor device receives a control signal corresponding to an output signal format of remote control codes necessary for controlling an electric device selected by a user.

Abstract: A multibit digital threshold comparator is disclosed which comprises a source of a multibit digital input signal representing a signed arithmetic value, and a source of a threshold signal. Means are provided for producing a magnitude representative signal. The magnitude representative signal produced has either the value of the input signal or that of the ones complement of the input signal depending upon the sign of the value of the input signal. A comparator compares the magnitude representative signal to the threshold signal. The comparator performs one of two comparisons depending upon the sign of the value of the input signal. First, if the value of the input signal is of a first sign, then the comparator produces a signal having a first state if the value of the magnitude representative signal is greater than the value of the threshold signal.

Abstract: A stem mold includes an improved first (upper) mold assembly and a conventional second (lower) mold assembly. The first mold assembly includes a conventional mold head and a plurality of lead-weights which are attached to one end of the mold head. The first mold assembly is improved by the inclusion of a novel first mold block which has a plurality of fillet recesses therein which communicate through guide openings with a plurality of buffer-pin-wells extending into a cavity in a second surface of the mold block. A novel lead-weight translator is disposed within the cavity in the mold block. The translator has a translator recess formed in one surface and a plurality of lead-weight apertures extending from the recess through the other surface of the translator. A pin holder is disposed within the translator recess. A plurality of pin apertures are formed through the pin holder and aligned with the buffer-pin-wells in the mold block and also with the lead-weight apertures in the translator.

Abstract: A video apparatus capable of operating at different line deflection frequencies incorporates a CRT electron gun assembly heater supply voltage circuit that maintains a constant rms voltage level independent of the line deflection frequency. The heater supply includes a transformer winding located on the line deflection driver transformer. The duty cycle of the developed AC voltage waveform remains substantially constant independent of the line deflection frequency, so that the AC voltage may be applied to the heater circuit.

Abstract: A sampled data tone control system, applicable for providing audio bass cut and boost control, includes a single variable multiplying circuit for determining the system variable response characteristics. Input samples are coupled to the multiplier which has its output connected to an integrator. The integrated samples are scaled by a constant and combined with the input samples to provide tone controlled signal.

Abstract: The present invention provides an improvement in color cathode-ray tubes. Such tubes include an electron gun for generating and directing three inline beams, a center beam and two side beams, along initially coplanar paths toward a screen of the tube. The gun includes a plurality of spaced electrodes which provide a first, a second and a third lens for focusing the electron beams. The first lens has a beam forming region for providing substantially symmetrical beams to the second lens. The improvement comprises the combination of the second and third lens. The second lens includes at least one electrode to provide asymmetrically-shaped beams. The potentials applied to the second lens refract electron beams emerging off-axes from the first lens toward the axes. The third lens is a low aberration main focusing lens which provides asymmetrically-shaped beams of substantially constant current density to the screen.

Abstract: Size control circuitry allows the selection of a number of different combinations of raster heights and widths for a video display apparatus. A raster size selection signal is decoded to determine one of a number of possible height and width combinations. The height is determined by varying the vertical size feedback signal to the vertical deflection circuits. The raster width is determined by varying the operation of a side pincushion correcting diode modulator circuit.

Abstract: A tuning system for tuning non-standard frequency RF television signals provided by cable distribution networks and television accessories conducts first and second consecutive searches by changing the local oscillator frequency. The first search is limited to search frequencies corresponding to predictable non-standard frequencies associated with the major cable distribution networks. The second search includes more search frequencies and extends over a wider frequency range than the first. During an auto-programming mode, in which active channels are identified, for memorization in a channel list portion of a memory, only the first search is conducted to minimize the required time.

Abstract: A deflection circuit for a video apparatus that operates at multiple line rate deflection frequencies includes an S-shaping correction circuit that provides proper S-shaping of the line deflection current at any of the video apparatus line rate operating frequencies. A first S-shaping capacitor is in series with the deflection winding and also in series with a transformer primary winding. The transformer secondary winding is coupled to one or more capacitors. The secondary winding side capacitors are coupled to the secondary winding circuit in response to a line rate frequency indicative signal in order to form a series combination of the primary and secondary side capacitors. The effective capacitance of the secondary side capacitor is then equal to the actual capacitance value increased by a factor determined by the transformer secondary to primary winding turns ratio.

Abstract: A first run supply voltage is generated, during a power-up mode of a television receiver power supply, by rectifying a retrace voltage in a flyback transformer of a horizontal output stage of the television receiver. The rectified voltage is coupled through a resistor and a diode to a power supply voltage receiving terminal of an integrated circuit that generates a horizontal rate drive signal. The drive signal provides switching timings to the output stage. A standby supply voltage is coupled, during a standby mode, to the terminal. A shunt regulator regulates the voltage at the terminal during both the power-up and standby modes. A transistor having a collector electrode that is coupled to the run supply voltage and a base electrode, that is coupled to the anode of the diode, generates a second run supply voltage that is temperature compensated at an emitter electrode of the transistor.

Abstract: A deflection circuit for a video apparatus is capable of operating at different horizontal rate frequencies in response to the incoming video information rate. In one embodiment, the deflection oscillator input voltage is varied in a cyclical manner to vary the oscillator frequency. When the oscillator frequency corresponds to the frequency of the incoming video information, the input voltage is maintained to maintain the desired oscillator frequency. In an alternate embodiment, a frequency to voltage converter generates the desired oscillator input voltage in response to the incoming video information rate.

Abstract: A degaussing apparatus for a video display includes a degaussing coil and a source of degaussing current. A switching means is coupled to the degaussing coil and to the source for providing a path for degaussing current between the source and coil during a degaussing operation. First and second PTC elements, functioning as degaussing current reducing means, are coupled to the degaussing coil and to the switching means. The switching means produces alternate coupling of the first and second PTC elements to the degaussing coil with respect to successive degaussing operations.

Abstract: A pair of locating washers are applied over the holes in the bottom mounting lugs of the kinescope. The washers have apertures which are precisely referenced with respect to the position of the kinescope screen by using a pair of oppositely-disposed screen locating marks. The TV cabinet, on the other hand, is equipped with a pair of tapered guiding posts on the inside front surfaces thereof, which are similarly referenced relative to the rectangular opening of the cabinet. When the kinescope is loaded into the cabinet, the cabinet guiding posts are received into the kinescope-mounted locating washers to assure registration between the kinescope screen and the cabinet opening. The kinescope is fixedly secured to the cabinet by a plurality of screws.

Abstract: A variable preemphasis/deemphasis network is disclosed which is coupled between audio input and output terminals. The network exhibits a family of transfer function response characteristics which vary between a full deemphasis characteristic H(f) and a full emphasis characteristic 1/H(f) in response to a control signal and exhibits complementary transfer function response characteristics in response to reciprocal valued control signals. The network includes a signal filter which determines the shape of the transfer function response characteristic, and a gain controlled amplifier which determines which one of the family of transfer function response characteristics is exhibited in response to the control signal.

Abstract: An on-screen character display system includes a tri-state character generator for generating a tri-state character signal having black portions corresponding to the leading and trailing edging portions of the character and a white portion corresponding to the body of the character and an inactive level when no character is to be displayed. To prevent the shielded cable used for coupling the tri-state character signals to video signal processing circuit from remaining charged to the black level corresponding to the trailing edging portion too long thereby creating a disturbing inequality between the widths of the edging portions, an auxiliary driver circuit is enabled to drive the shielded cable toward the inactive level when the character is supposed to end.

Abstract: Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K).sup.2) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K).sup.2 is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.