Abstract: There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.

Abstract: An electromagnetic actuator for a data disc drive having a carriage on which is mounted one or more read/write heads for cooperation with a data disc. The carriage is supported in the housing for movement on an axis that is oriented radially of the disc. The end of the carriage remote from the read/write head is of hollow rectangular cross-sectional shape; there is a voice coil mounted on the end of the carriage. A magnetic housing defines a cavity in alignment with the carriage and the coil so that the carriage and coil can move within the cavity. The housing is constructed of magnetic material, and in magnetic circuit with the housing is at least one permanent magnet. The permanent magnet has a surface that confronts the path along which the coil moves.

Abstract: There is described a circuit which controls or arbitrates access to a memory unit among a plurality of data processing units. The circuit also manages pointers to different sections of the memory upon a simple one byte request. The circuit also protects the code of the data processing units from illegal write entries.

Abstract: There is described a unique apparatus for exchanging commands and data via a dedicated memory which has ports connected to the data and address busses of two different microprocessors. The system operates even though the microprocessors have different word lengths, e.g. a sixteen bit processor and an eight bit processor. The system permits interfacing between the microprocessors with different bit size words and allows each of the microprocessors to treat the exchange memory as part of its own memory space without locking one microprocessor off of a shared bus.

Abstract: There is described a register circuit which is utilized with a system having the capability of interfacing between two data processing units which may have different operating speeds or data rate handling capabilities. The register permits writing and reading of data in a manner which is independent of the operating speed of the processing unit. The register provides pointers which selectively permit reading and/or writing in a prescribed manner but, at the same time, prevents writing or reading in a forbidden condition (i.e., writing in a full register or reading from an empty register).

Abstract: A register circuit which is used to asynchronously monitor any data or logical function (or functions) and be able to retain the status of the monitoring until the register is interrogated whereupon the register is automatically reset and able to receive or monitor another status signal.

Abstract: An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic "exit" microcommand to be interpreted either as a "return" or a "decode" depending upon the state of the subroutine stack.

Abstract: There is provided a circuit which automatically selects one or the other of at least two contending processor circuits and selectively grants the selected processor circuit access to an exchange memory in a regulated and prioritized manner.

Abstract: A gate generator circuit for receiving a pulse type input data signal, wherein the locations of the pulse peaks are representative of the data, includes a comparator for comparing voltage levels of the pulses of the input signal with a reference voltage applied to the comparator so as to generate rectangular pulses, the reference voltage being varied in a controlled manner to assure that each rectangular pulse has at least a prescribed minimum time duration. A tapped delay line and logic circuits coupled to selected taps thereof respond to the rectangular pulses to produce a gating pulse signal by symmetrically expanding the rectangular pulses if the pulse widths thereof are less than or equal to a predetermined time duration and by transmitting the rectangular pulses unchanged in pulse widths if the pulse widths thereof are greater than the predetermined time duration.

Abstract: A spindle assembly comprising a hub rotatably supported about a fixed shaft by a pair of ball bearings disposed along the shaft and having a preload spring compressed between a member on the shaft and the inner race of one of the bearings to establish back to back mounting of the bearings for holding the shaft axis in collinear alignment with the centerline of the hub which includes inner and outer laterally connected cylinders with the shaft extending through the inner cylinder and the outer cylinder being adapted for mounting thereabout of members to be rotated.

Abstract: A circuit is provided for detecting a low power condition which is undesirable and effectively turns off a computer system to prevent incorrect operation thereof. The circuit does not turn on the computer system until the correct power condition is achieved. The circuit is also sensitive to the power condition to establish the time duration permissible for causing the computer system to be turned off.

Abstract: In a data recovery system, encoded variable spaced digital data is recovered by provision of variable width windows which are expanded or narrowed so as to tend to center upon the expected occurrence of valid data based on knowledge of the contents of the current or the immediately preceding timing units and of characteristics of the encoding scheme. The system employs pulse-to-pulse synchronization without modifying the underlying synchronization of the system such that the first pulse of a two-pulse series serves as a window size reference for an immediately subsequent pulse. The window for a reference pulse is expanded at its trailing edge if, for example, the reference pulse is delayed beyond the tolerance of the detection system. The leading edge of a window for the subsequent pulse is expanded if no pulse occurs within a minimum period following the reference pulse.

Abstract: A memory system for a data processing apparatus including a stack and a stack image memory which provides either sequential or simultaneous access to information contained on the stack. A stack control logic unit is responsive to a stack instruction so that information written into the stack is simultaneously written into one or more random access memory units. Moreover, a sequence of information items read sequentially from the stack may be read simultaneously from different random access memory units. The memory address unit is preferably implemented with programmable read-only memories.

Abstract: This invention relates to a system for determining an effective address based upon a calculation performed on address information. Depending upon the result of the calculation firmware or hardware will control further operation of the system.

Abstract: A locking and bracing apparatus, comprising a vertically movable interlock bar and a horizontally movable outrigger-type support brace, is mounted to a cabinet having a drawer. When the brace is in a stored position within the cabinet or in any position intermediate the stored position and a fully extended position, a peg which is on the interlock bar and slidably rides over the brace keeps the interlock bar in a raised position whereby the drawer is locked in a closed position within the cabinet. When the brace is in the fully extended position to support the cabinet from tipping, the peg is disposed in a hole formed in the brace so that the brace is locked in the extended position and the interlock bar is in a lowered position whereby the drawer is unlocked. Thereafter, if the drawer is pulled outward from the cabinet, the interlock bar is blocked by the drawer from being moved from the lowered position so that the brace remains locked in the extended position.

Abstract: An automatic gain control circuit comprising a gain-controlled amplifier for receiving a variable amplitude, pulse-type input signal to produce a substantially constant amplitude, pulse-type output signal which is applied to a feedback circuit for comparison with a predetermined reference voltage to generate a control voltage to set the gain of the amplifier. A voltage limiter included in the feedback circuit clips the pulse peaks of the output signal whenever the peaks exceed a predetermined amplitude so that the gain of the amplifier is reduced in a prescribed manner to preclude output signal dropout. A peak detector and a filter included in the feedback circuit are capable of operating in fast and slow modes. When operating in the fast mode, the peak detector responds essentially to each pulse peak of the output signal and the filter has a wide bandwidth so that the automatic gain control circuit operates with a prescribed fast time response.

Abstract: A pulse improvement circuit for a magnetic readback system produces a data representative signal having symmetrical, equal-amplitude pulses of limited time widths. The circuit includes an equalizer made in accordance to a final transfer function produced as a result of a mathematical convolution of first and second transfer functions. The first transfer function is based on the theory of a matched filter for receiving a signal having data representative and non-white noise pulses contained therein to produce a filter signal having maximum signal to noise ratio. The second transfer function is based on the theory of a Papoulis window function for slimming the pulses contained in the filter signal. A specific circuit implementation of the final transfer function is an eight-pole, inductor-capacitor, ladder network for amplitude equalization coupled to an inductor-capacitor, lattice network including first and second order sections for phase equalization.

Abstract: There is shown and described a method and apparatus for using a "block move" instruction in a microprocessor to execute the direct memory access (DMA) data transfer function between a microprocessor and a minicomputer. The instruction permits an apparent data transfer in the memory of the microprocessor to be utilized to transfer data to the memory in the minicomputer. Little or no additional hardware over existing systems is required.

Abstract: There is disclosed a circuit which is capable of performing a square root function in a floating point processor in such a manner that the speed of operation is increased by approximately 50%.

Abstract: There is described a floating point processor architecture which permits multiple bit shifting over strings of binary 1's and strings of binary O's in a single machine cycle. During a multiply operation, an MQ register (arranged in parallel) which stored the multiplier, shifts the multiplier out for decoding at a rate comparable to the rate at which the partial product is shifted. This is made possible by using a parallel MQ register so that two bits may be shifted per clock cycle. This architecture permits extremely fast multiplication by using a multiple bit shift architecture while minimizing hardware requirements.