Abstract: A tachometer for generating a velocity signal in a data disc pack servo system comprising a sampling pulse generator for producing pulses that are spaced from one another by a constant amount representative of a distance increment of radial movement of a servo head in the system, a timer for measuring the time between the sampling pulses, the timer including a clock pulse source and a counter which is started by one sampling pulse and reset by the next succeeding sampling pulse so that the digital output thereof is proportional to time and a computer for computing average velocity by deriving the quotient of the distance increment divided by the time required for the servo head to traverse such distance increment.

Abstract: A binary data encoding and recovery technique for which the encoding is carried out by separating the binary data into successive data words each containing an equivalent number of data bits, generating one or more code signals representative of each data word where each code signal corresponds to a signal change at one of a plurality of signal change positions in a data cell associated with the data word and is spaced from adjacent signal changes in the data cell by at least a prescribed minimum amount, and assuring that succeeding signal changes occurring in a sequence of data cells are spaced at least the prescribed minimum amount by determining whether a signal change in one data cell would be spaced less than the prescribed minimum amount from a signal change in an adjacent data cell and in such event providing for the code signals related to such signal changes to be merged into a code signal corresponding to a signal change positioned at the boundary of the adjacent data cells so that the prescribed mi

Abstract: A tapped delay line (38) terminated with its characteristic impedance at both ends is connected to receive a differential input signal in intermediate taps (27, 29) of a delay line. Delay line taps (25, 27, 29, 31), as well as ends (21, 23) are connected symmetrically to two pair of summing networks (59, 61 and 83, 85) where voltage signal components having different delays from the input signal are linearly combined. One pair of summing networks (59, 61) produces a balanced differential output signal which is an amplitude equalized and differentiated version of the input signal, while the other pair of summing networks (83, 85) produces another balanced differential output signal which is a different amplitude equalized version of the input signal. Each version is needed in one of the channels of a dual channel signal detector for detecting the peaks of the variable amplitude input signal.

Abstract: A circuit for controlling the charge and the voltage of a substrate for use with integrated circuit devices.

Abstract: An improved shielded ribbon cable arranged to expedite termination of the shield for grounding the shield. There is an isolator strip placed during fabrication of the cable between the conductor array and the shield; the isolator strip prevents flow of plasticized insulating material between the cover sheet and the conductor array, which usually occurs through the interstices in the shield, so that the shield can be readily separated from the conductor array to permit termination of the shield without jeopardizing the integrity of the insulation on the conductor array.

Abstract: A power driver control circuit (38) provides control signals (44, 46, 48, 50, 52, 54) for switching transistors in a power driver (56) for an electromagnetic actuator (11) of the type used for controlling a servo head (12) in a closed loop servo system. The control circuit includes variable time delay circuits (70, 71) connected to threshold detectors (74, 84) so that dead zones can be created when the servo error signal changes polarity thereby isolating the switches and preventing switch burn-out.

Abstract: There is described a map memory system with a time-multiplexed memory address bus wherein the mapping function is performed on the high order address bits in parallel with the output of the low order address bits on the time multiplex bus.

Abstract: In a disc pack data storage system that has a plurality of discs and a plurality of heads for coaction with the discs, a tachometer for producing a signal indicative of the radial speed of the heads with respect to the discs. At least one of the disc surfaces is a servo surface and at least one of the heads is a servo head so that in response to radial movement of the servo head a triangular position signal is produced. Sampling pulses indicative of specific radial positions of the head are derived from the position signal so that the time required for the head to move between two positions represented by adjacent sampling pulses is inversely proportional to radial head speed. Control and computing circuitry measures the time between adjacent pulses by providing a clock pulse source and counting the number of clock pulses that occur between adjacent sampling pulses.

Abstract: An electromagnetic linear actuator for positioning a transducer over locations on a rotating magnetic recording disk comprising an actuator housing used as a stationary base for supporting various parts; a coil and cart assembly including a cart, having a rectangular cross section and tubular in construction, adapted at one end to support the transducer, and including a direct current coil with a cross section matching that of the cart mounted at the other end thereof; magnetic means affixed to the actuator housing having an air gap for receiving the coil so that the coil is immersed in a magnetic field; and support means affixed to the actuator housing engaging the surfaces of the cart and disposed about the center of gravity of a moving-mass assembly consisting of the coil and cart assembly and the transducer.

Abstract: As an aid in counting servo tracks in a position servo system, a position window detector (30) which normally provides coarse and fine pulses to counting logic (53) also provides fine pulses to a reset switch (45) of a tachometer signal integrator means (33), resetting the integrator once for each track. In the event of position signal drop-out wherein coarse pulses are not properly generated, a threshold detection means (43) senses when the output of the integrator reaches a threshold level and produces a threshold reached signal which is transmitted to counting logic means (53) for incrementing a track counter (61).

Abstract: There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.

Abstract: This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry, systems or the like wherein elongated information trains represented by multiple words of multiple bits are multiplied by equally long information trains. In many cases, the trains comprise a plurality of trailing zeros which, in accordance with the operation of this circuit, can be detected whereby the multiplication operation can be significantly speeded by avoiding unnecessary multiplication by zeros without loss of accuracy.

Abstract: A disk drive control system incorporating an internal microprocessor and internal testing capabilities. The disk drive control system is capable of simulating drive operation without carriage motion so as to test substantially all functional subsystems of the disk drive. The test technique comprises the exercising of subsystems and a diagnosis of operations according to a hierarchy of interdependence of subsystem operation.

Abstract: A signal amplitude equalizer circuit, having linear phase, for reforming high density magnetically recorded read-back signals to remove peak shift and the resulting errors caused thereby. The equalizer circuit employs series balanced differential amplifier circuits in connection with properly terminated delay lines across the amplifier output terminals to provide an adjustable transfer function that transforms the readhead signal, that follows an exponential frequency spectra curve, into a cosine power frequency spectra curve which, in the time domain, possesses a sufficiently narrow base to eliminate peak shift and its resulting amplitude decay.

Abstract: A tapped delay line (39) terminated with its characteristic impedance at both ends is connected to receive a differential input signal across ends (35, 37) of the delay line. Delay line taps 41, 43), as well as ends, are connected symmetrically to a pair of summing networks (71, 73) where voltage signal components having different delays from the input signal are linearly combined. The output waveforms from both summing networks are combined to provide a balanced differential signal that has been both amplitude equalized and differentiated from the input signal with variable amplitude for use in a signal detector (87, 89) that requires such a shaped signal waveform.

Abstract: An electronic tachometer that includes an integrator for producing a speed signal by integrating a signal representative of acceleration of a body and a differentiator for producing a speed signal by differentiating a signal representative of the position of the body, the differentiator being formed by a passive RC circuit and operatively associated with circuitry for alternately supplying to the differentiator two signals representative of position, one of which is inverted so that signals of a single polarity are supplied to the differentiator, and further circuitry for connecting the differentiator output to the integrator feedback circuitry so as periodically to update or reset the speed signal produced by the integrator, which is formed by an operational amplifier having a capacitive feedback which is shunted by a resistor when the differentiator output is active to update the integrator.

Abstract: There is provided an error detection and correction circuit which is optimized in terms of the operation, part count and the like. This invention includes parity generator circuitry to generate parity signals in accordance with a variation of the Hamming Code in response to the application of a plurality of input data bits. The parity signals are applied to a memory bus during a write cycle. During a read cycle, the parity generators produce a parity error signal, if appropriate, to indicate an error in parity. The error correction circuit receives the data bits from the memory (or memory bus) along with the parity error signals generated by the parity generator circuit portion. The data signals and parity error signals are gated together and supplied to Exclusive-OR gates. If an error is indicated by the level of the input signal, the Exclusive-OR gate converts the signal thereby correcting the erroneous data bit.

Abstract: In a digital information storage system or the like, start up power sequencing for independently operable machines such as disk drives each equipped with a microprocessing unit is provided through a simplified power sequencing circuit. The power sequencing circuit is operatively coupled with an independent preprogrammable micropocessing unit in each machine and to a single control line common to all disk drives. The microprocessing unit is preprogrammed to interact with the power sequencing circuit to provide Enable/Disable signals to the control line and to sense the state of the control line. In particular, the microprocessing unit executes a preprogrammed sequence of steps in interaction with the control line to sequence the start-up of each spindle motor irrespective of the number of disk drives coupled to the control line, thereby preventing electrical power overload.

Abstract: An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. Contending controllers resolve priority among themselves by monitoring the priority bus. If a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus. The highest priority controller then activates an acknowledge signal and places its device address on a bidirectional data bus in response to a ready signal from the channel.

Abstract: Magnetic recording apparatus including signal equalization means for recording data so as to obtain read pulses therefrom which are symmetrical about their peak and substantially narrowed at both the base and half amplitude points whereby increased packing density may be achieved without attendant peak shift, the equalization being provided by means for generating an ac bias signal in conjunction with data transitions and associated equalizer transitions referenced to the bias signal for application to magnetic recording means.