Abstract: A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

Abstract: Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. MCD circuits improve response to process, voltage and temperature (PVT) variations.

Abstract: A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

Abstract: Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target modules that are physically located in each design section of a device that uses configuration storage. A distributed configuration master module, physically located near the host interface, controls access into and out of each target module via a distributed configuration bus. The creation of each storage array in the distributed configuration storage can be automated using a scripting tool that converts each register specification into hardware description language code.

Abstract: In a system for chemical analysis, an RF-driven plasma ionization device including a pair of spaced-apart and plasma-isolated electrodes, the electrodes are connected to a power source wherein the electrodes act as plates of a capacitor of a resonant circuit, the gas electrically discharges and creates a plasma of both positive and negative ions, and the voltage is applied as a continuous alternating waveform or as a series of pulses, such as a packet waveform.

Abstract: A system estimates flow parameters associated with a fluid flow encountering a bluff body. The system includes multiple sensors distributed on a surface of a bluff body. The system further includes input circuitry and a sensor processing unit. The input circuitry receives a signal from each of the multiple sensors. The sensor processing unit determines noise levels associated with each of the multiple sensors due to the fluid flow encountering the bluff body. The sensor processing unit further assigns weights to each of the multiple sensors based on the determined noise levels and estimates the fluid flow direction based on the assigned weights.

Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: The present invention relates to novel compositions of therapeutic cyclodextrin containing polymeric compounds designed as a carrier for small molecule therapeutics delivery and pharmaceutical compositions thereof. These cyclodextrin-containing polymers improve drug stability and solubility, and reduce toxicity of the small molecule therapeutic when used in vivo. Furthermore, by selecting from a variety of linker groups and targeting ligands the polymers present methods for controlled delivery of the therapeutic agents. The invention also relates to methods of treating subjects with the therapeutic compositions described herein. The invention further relates to methods for conducting pharmaceutical business comprising manufacturing, licensing, or distributing kits containing or relating to the polymeric compounds described herein.

Abstract: The invention relates to mechanical actuators for forming images on a display. The actuators include two mechanically compliant electrodes.

Abstract: An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

Abstract: A method for applying surface modifications in at least two patterns that differ in spectral emissivity by known amounts. The patterns form an information-encoding sequence of transitions of differential emissivity along a scan path over the patterns, that encodes a set of information. This information is decoded by a scanner sensitive to emissivity in the given portion of the electromagnetic spectrum, and sensitive to transitions in emissivity of the known amounts, when scanned along the scan path, combined with knowledge of the expected emissivity values of the patterns. This provides secure informational marking of articles and documents, including mail. The patterns may be visible, or hidden, but the emissivity values are not duplicated by standard office equipment, so authenticity of the patterns can be determined using the special emissivity scanner.

Abstract: Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.

Abstract: Systems and methods for performing neighbor discovery in a network (100) including a number of nodes are provided. A first node (110) in the network (100) generates a spread signal for alerting other nodes in the network (100) of the presence of the first node (110). The first node (110) broadcasts the signal and a second node (120) receives the signal and calculates an energy associated with the received signal. The second node (120) also determines whether the energy is greater than a threshold and identifies the first node (110) as a neighbor node when the energy is greater than the threshold.

Abstract: The application discloses novel polypeptides and nucleic acids involved in a variety of biological processes, including viral reproduction. Related methods and compositions are also described.